Infineon Technologies Ag

Pramod Acharya

Stefan Dietrich

Sabine Kieser

Peter Schroegmeier

Andreas T&auml;uber

Christian Weis

Peter Schr&ouml;gmeier

Peter Schrögmeier

Gerald Sellmair

Ravikiran Lakshman

Prashant Kashinkunti

A cell-based integrated circuit comprises a first supply voltage terminal and a second supply voltage terminal. A standard cell comprising a thyristor circuit comprising a first input inputs the first supply voltage. A second input inputs the second supply voltage. A first output outputs a first output voltage corresponding to the first supply voltage and a second output to output a second output voltage corresponding to the second supply voltage.

Cell-based integrated circuit and a method of operating a thyristor circuit in a standard cell of a cell-based integrated circuit

A cell based integrated circuit chip includes a top voltage supply rail and a bottom voltage supply rail and a plurality of metal layers defining at least one filler cell. The filler cell is formed by a first field effect transistor of a first type conductivity, typically an n-channel MOSFET. The source or drain electrodes of the n-channel MOSFET are arranged to as act as a capacitor with respect to the bottom voltage supply rail and to which at least one of the source and drain electrodes is connected. A second field effect transistor of an opposite-type conductivity to the first field effect transistor, typically a p-channel MOSFET, is also provided. The source or drain electrodes of the p-channel MOSFET are connected in series between the top voltage supply rail and a gate electrode of the n-channel MOSFET. The gate electrode of the p-channel MOSFET is connected to a source of ground potential via a resistor.

High-efficiency filler cell with switchable, integrated buffer capacitance for high frequency applications

Implementations are presented herein that include a level shifter circuit.

Level Shifter, standard cell, system and method for level shifting

A method of switching on a voltage supply of a voltage domain of a semiconductor circuit includes switching, initially, a first switchable element, via which elements of the voltage domain are connected to a supply voltage of the semiconductor circuit, to a conductive state. The method includes switching, after a predetermined period of time, a second switchable element, via which elements of the voltage domain are connected to the supply voltage of the semiconductor circuit, to a conductive state. The driving capacity of the first switchable element is less than the driving capacity of the second switchable element.

Switching voltage supply of voltage domain of semiconductor circuit

The invention is aimed at providing a novel semi-conductor component, as well as a novel process for reading test data. There is a process for reading test data is made available, including reading test data generated during a semi-conductor component test procedure from at least one test data register of a semi-conductor component, storing the test data in at least one useful data memory cell provided on the semi-conductor component, and reading the test data from the at least one useful data memory cell.

Comparator and method for amplifying an input signal

An integrated circuit includes a processing circuit with at least one first and second input connected to a connection for obtaining a control clock. The first and second input are for receiving at least one first and second clock signal that each are derived from the control clock and that are shifted in phase with respect to one another. A third clock signal is generated from the first and second clock signals, and is at a higher frequency than the frequency of the control clock for controlling operation of the circuit. The third clock signal is output at an output. Since the frequency of the third clock signal is greater than the frequency of the control clock, the circuit can, however, be operated over its full frequency range, by using a test unit to supply a control clock at a lower frequency.

Integrated circuit and method for operating the integrated circuit

Latency time circuit for an S-DRAM, which is clocked by a high-frequency clock signal for producing a delayed data enable control signal for synchronous data transfer through a data path of the S-DRAM, having at least one controllable latency time generator for delaying a decoded data enable control signal with an adjustable latency time, characterized by at least one comparison circuit, which compares the cycle time of the high-frequency clock signal with a predetermined decoding time and by a signal delay circuit which can be switched on by means of the comparison circuit in order to delay the decoded data enable control signal with a predetermined delay time, in which the signal delay circuit is switched on by the comparison circuit when the cycle time of the clock signal is in a limit time region which is located about the predetermined decoding time.

Latency time circuit for an S-DRAM

Latency time circuit for an S-DRAM ( ), which is clocked by a high-frequency clock signal (CLK), for producing a delayed data enable signal for synchronous data transfer through a data path ( ) of the S-DRAM ( ), having a controllable latency time generator ( ) for delaying a decoded external data enable signal (PAR) with an adjustable latency time, which a comparison circuit ( ) which compares a cycle time (t ) of the high-frequency clock signal (CLK) with a predetermined signal delay time of the data path ( ), and reduces the latency time of the latency time generator ( ) by the cycle time if the signal delay time of the data path ( ) is greater than the cycle time (t ) of the clock signal (CLK)

Latency time switch for an S-DRAM

DDR memory and storage method

The voltage supply provides voltages to an electronic circuit requiring at least two different supply voltages. A plurality of standby supply voltages with different levels are obtained from the highest supply voltage with the aid of a voltage divider.

Standby voltage controller and voltage divider in a configuration for supplying voltages to an electronic circuit

An integrated circuit containing a number of subcircuits is described. Each of the subcircuits contains a driver circuit for driving in each case one controllable voltage source on the basis of a reference value. The driver circuit has a memory unit for storing a reference value and a terminal for outputting a first reference value or for inputting a second reference value. A signal line, which is used for transmitting a signal, is connected to the terminal of the driver circuit of each of the subcircuits. The driving by the driver circuit is effected in each subcircuit on the basis of a common reference value that is transmitted via the signal line. Thus, the time needed for setting the reference values for all subcircuits is relatively short.

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Munich, Germany

Pramod Acharya