Apple Inc.

Prakhar Malhotra

Matthias Knoth

Constantin Pistol

Dmitriy B Solomonov

Jaidev P Patwardhan

Matthew C Widmann

Shekhar S Srikantaiah

An apparatus includes a processor circuit that includes a memory circuit, one or more processor cores, and a debug circuit. The debug circuit may be configured, in response to activation of a trace mode to record information indicative of instructions executing on the one or more processor cores, to write a trace data stream to the memory circuit that includes trace data collected on the instructions executing on the one or more processor cores. In response to a particular instruction within one of the processor cores specifying a write of a data value to an architecturally visible trace register, the debug circuit may be further configured to output the data value to the trace data stream as part of executing the particular instruction.

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San Jose, CA, United States of America

Prakhar Malhotra