Microsemi Soc Corporation

Prakash Reddy

Ashwin Murali

Pinninti Arjun

A method for detecting failure of speed measurement of a multi-phase AC motor includes (1) sensing current drawn by the motor, (2) sensing voltage magnitude supplied to the motor, (3) measuring motor speed, (4) calculating motor speed, (5) determining whether the difference between the measured motor speed and the calculated motor speed is greater than a predetermined threshold, if the difference between the measured motor speed and the calculated motor speed is not greater than a predetermined threshold, repeating (1) through (5), if the difference between the measured motor speed and the calculated motor speed is greater than a predetermined threshold, indicating a fault, if a fault is indicated, performing a predetermined number of restart attempts, if the motor is successfully restarted, repeating (1) through (5), if the motor is not successfully restarted, indicating a restart failure.

Circuit and method to detect failure of speed estimation/speed measurement of a multi-phase AC motor

A digital phased lock loop includes a digital controlled oscillator configured to produce an output signal at an output signal frequency, and a phase comparator configured to compare the output signal or a signal derived from the output signal, with a reference signal at a reference signal frequency or a signal derived from the reference signal to produce a phase error signal. A first loop filter produces a first control signal for the digital controlled oscillator. A frequency error measuring circuit produces a frequency error signal that directly represents a frequency difference between the output signal frequency and the reference signal frequency. A second loop filter produces a second control signal for the digital controlled oscillator from an output of the frequency error measuring circuit. A circuit combines the first and second control signals and providing the combined control signals to the digital controlled oscillator.

Hybrid phase locked loop having wide locking range

A digital phased lock loop includes a digital controlled oscillator configured to produce an output signal at a frequency. A phase comparator compares the output signal, or a signal derived therefrom, with a reference signal to produce a phase error signal. A first loop filter produces a first control signal for the digital controlled oscillator from an output of the phase comparator. A frequency error measuring circuit coupled to the output of the phase comparator produces a frequency error signal. A second loop filter produces a second control signal for the digital controlled oscillator from an output of the frequency error measuring circuit. A circuit combines the first and second control signals and provides the combined control signals to the digital controlled oscillator.

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Hyderabad Telangana, India

Prakash Reddy