Virage Logic Corporation

Synopsys, Inc.

Prakash Ravikumar Bhatia

Subramani Kengeri

Deepak Sabharwal

Sanjiv Kainth

Michael Tooher

Shreekanth Sampigethaya

Ashish Akhilesh

Yogesh Malviya

A transient voltage collapse circuit provides a reference voltage for an SRAM (static random access memory). The SRAM receives a first reference voltage and a second reference voltage higher than the first reference voltage. The transient voltage collapse circuit provides the first reference voltage to the SRAM via a voltage supply line. The transient voltage collapse circuit maintains the voltage supply line at a first voltage level during a power save mode of the SRAM. The transient voltage collapse circuit increases the voltage of the voltage supply line during a write operation of the SRAM. The increase in the voltage of the supply line reduces the gap between first reference voltage and the second reference voltage, thereby assisting with the write operation of the SRAM.

Write assist circuit integrated with leakage reduction circuit of a static random access memory for increasing the low voltage supply during write operations

In one embodiment, a static random access memory (SRAM) is operable with first voltage and second voltages and includes a plurality of SRAM cells arranged in rows and columns, each SRAM cell being coupled to a respective wordline, respective complementary bitlines, and a source line and a control circuit connected between the source line and the second voltage. The control circuit is selectively operable in a working mode in which data in the plurality of SRAM cells can be accessed, a sleep mode is which data is retained but leakage is reduced and a shutdown mode in which the source line is allowed to float to a level that is substantially equal to the first voltage.

Memory leakage control circuit and method

A method and system for testing the individual memory cells of a volatile memory cell array (e.g., SRAM) for data retention faults are described. In one embodiment of the invention, adjacent memory cells connected by a pair of common bit-lines are written with opposite, or complementary, data, for example, logical '0' and logical '1'. Next, the two memory cells are subjected to a stress condition by pre-charging the common bit-lines connecting the two adjacent memory cells, and then simultaneously asserting the word-line of each memory cell. Finally, the data in each cell is read and compared with the data written to the cell prior to generating the stress condition.

Method and system for accelerated detection of weak bits in an SRAM memory device

A multi-port memory device with an array of single-port memory cells is disclosed. According to one embodiment of the invention, the multi-port memory device has N number of memory ports, and is capable of performing any combination of N number of read/write operations during a single cycle of an externally generated core clock signal, without the need of any other externally generated clocking signals.

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Fremont, CA, United States of America

Prakash Ravikumar Bhatia