Micron Technology Incorporated

Intel Corporation

Lodestar Licensing Group LLC

Prakash Rau Mokhna Rau

Anilkumar Chandolu

Christopher J Larsen

S M Istiaque Hossain

Tom Jibu John

Arun Kumar Dhayalan

David A Daycock

Gordon A Haller

Darwin A Clampitt

Matthew Park

Sri Sai Sivakumar Vegunta

David Daycock

John B Matovu

Jun Zhao

Wesley O McKinsey

Lifang Xu

Indra V Chary

Jian Li

Matthew J King

Albert Fayrushin

Brett D Lowe

Yi Hu

Harsh Narendrakumar Jain

Damir Fazil

Gowrisankar Damarla

Merri Lyn Carlson

Joel D Peterson

Kye Hyun Baek

Rokibul Islam

George Matamis

John Mark Meldrim

Kunal Shrotri

Christopher W Petz

Wei Yeeng Ng

Rithu K Bhonsle

Saurabh Keshav

Kevin R Gast

Shashank Saraf

Gowrisankar Damaria

Wesly McKinsey

Philip M Campbell

Sm Istiaque Hossain

An electronic device comprising a lower deck and an upper deck adjacent to a source. Each of the lower deck and the upper deck comprise tiers of alternating conductive materials and dielectric materials. Each of the lower deck and the upper deck also comprise an array region and one or more non-array regions. Memory pillars are in the lower deck and the upper deck of the array region and the memory pillars are configured to be operably coupled to the source. Dummy pillars are in the upper deck of the one or more non-array regions and the dummy pillars are configured to be electrically isolated from the source. Another conductive material is in the upper deck and the lower deck of the one or more non-array regions. Additional electronic devices and related systems and methods of forming an electronic device are also disclosed.

Electronic devices including pillars in array regions and non-array regions

An electronic device comprising lower and upper decks adjacent to a source. The lower and upper decks comprise tiers of alternating conductive materials and dielectric materials. Memory pillars in the lower and upper decks are configured to be operably coupled to the source. The memory pillars comprise contact plugs in the upper deck, cell films in the lower and upper decks, and fill materials in the lower and upper decks. The cell films in the upper deck are adjacent to the contact plugs and the fill materials in the upper deck are adjacent to the contact plugs. Dummy pillars are in a central region of the lower deck and the upper deck. The dummy pillars comprise an oxide material in the upper deck, the oxide material contacting the contact plugs and the fill materials. Additional electronic devices and related systems and methods are also disclosed.

Electronic devices comprising memory pillars and dummy pillars including an oxide material, and related systems and methods

A method used in forming a memory array comprising strings of memory cells and operative through-array-vias (TAVs) comprises forming a stack comprising vertically-alternating insulative tiers and conductive tiers. The stack comprises a TAV region and an operative memory-cell-string region. Operative channel-material strings are formed in the stack in the operative memory-cell-string region and dummy channel-material strings are formed in the stack in the TAV region. At least a majority of channel material of the dummy channel-material strings is replaced in the TAV region with insulator material and operative TAVs are formed in the TAV region. Other methods and structures independent of method are disclosed.

Memory arrays and methods used in forming a memory array comprising strings of memory cells and operative through-array-vias

Some embodiments include an integrated assembly having a first deck. The first deck has first memory cell levels alternating with first insulative levels. A second deck is over the first deck. The second deck has second memory cell levels alternating with second insulative levels. A cell-material-pillar passes through the first and second decks. Memory cells are along the first and second memory cell levels and include regions of the cell-material-pillar. An intermediate level is between the first and second decks. The intermediate level includes a buffer region adjacent the cell-material-pillar. The buffer region includes a composition different from the first and second insulative materials, and different from the first and second conductive regions. Some embodiments include methods of forming integrated assemblies.

Integrated assemblies, and methods of forming integrated assemblies

A method used in forming a memory array comprising strings of memory cells and operative through-array-vias (TAVs) comprises forming a stack comprising vertically-alternating insulative tiers and conductive tiers. The stack comprises a TAV region and an operative memory-cell-string region. The TAV region comprises spaced operative TAV areas. Operative channel-material strings are formed in the stack in the operative memory-cell-string region and dummy channel-material strings are formed in the stack in the TAV region laterally outside of and not within the operative TAV areas. Operative TAVs are formed in individual of the spaced operative TAV areas in the TAV region. Other methods and structure independent of method are disclosed.

Electronic devices including pillars in array regions and non-array regions, and related systems and methods

A method used in forming a memory array comprising strings of memory cells comprises forming a stack comprising vertically-alternating first tiers and second tiers comprising memory-block regions having channel-material strings therein. Conductor-material contacts are directly against the channel material of individual of the channel-material strings. First insulator material is formed directly above the conductor-material contacts. The first insulator material comprises at least one of (a) and (b), where (a): silicon, nitrogen, and one or more of carbon, oxygen, boron, and phosphorus, and (b): silicon carbide. Second insulator material is formed directly above the first insulator material and the conductor-material contacts. The second insulator material is devoid of each of the (a) and (b). Third insulator material is formed directly above the second insulator material, the first insulator material, and the conductor-material contacts. The third insulator material comprises at least one of the (a) and (b). At least one horizontally-elongated isolation structure is formed in the first and second insulator materials and in a top part of the stack in individual of the memory-block regions. Additional methods, including structure independent of method, are disclosed.

Memory arrays and methods used in forming a memory array

A solid state memory component can include a plurality of bit lines, a source line, and a plurality of non-functional memory pillars. Each non-functional memory pillar is electrically isolated from one or both of the plurality of bit lines and the source line. A solid state memory component can include a plurality of pillars located in a periphery portion of the solid state memory component, and memory cells adjacent to each of the pillars. Associated systems and methods are also disclosed.

Solid state memory component

3D NAND memory cells can include a source layer, a dielectric layer disposed on the source layer, and a select gate source (SGS) layer disposed on the dielectric layer. A plurality of alternating layers of conducting material and insulating material can be disposed on the SGS layer. A conductive channel can be formed within a cell pillar trench. The conductive channel can be in contact with the source layer and the plurality of alternating layers. The cell pillar trench can be positioned in a substantially perpendicular orientation with respect to the plurality of alternating layers.

Flash memory cells

Solid state memory technology is disclosed. A solid state memory component can include a plurality of bit lines, a source line, and a plurality of non-functional memory pillars. Each non-functional memory pillar is electrically isolated from one or both of the plurality of bit lines and the source line. A solid state memory component can include a plurality of pillars located in a periphery portion of the solid state memory component, and memory cells adjacent to each of the pillars. Associated systems and methods are also disclosed.

Growing community of inventors

Boise, ID, United States of America

Prakash Rau Mokhna Rau