Intel Corporation

Prakash Math

Matthew C Merten

Robert S Chappell

Martin Guy Dixon

Konrad K Lai

Ravi Rajwar

Alexandre J Farcy

Rajesh S Parthasarathy

David W Burns

Vijaykumar Balaram Kadgi

Ilhyun Kim

Raanan Sade

Shlomo Raikin

Igor Yanover

Beeman C Strong

Sebastien Hily

Morris Marden

Michael D Tucknott

Pankaj Raghuvanshi

Michael S Bair

Leslie A Ong

An apparatus and method is described herein for providing robust speculative code section abort control mechanisms. Hardware is able to track speculative code region abort events, conditions, and/or scenarios, such as an explicit abort instruction, a data conflict, a speculative timer expiration, a disallowed instruction attribute or type, etc. And hardware, firmware, software, or a combination thereof makes an abort determination based on the tracked abort events. As an example, hardware may make an initial abort determination based on one or more predefined events or choose to pass the event information up to a firmware or software handler to make such an abort determination. Upon determining an abort of a speculative code region is to be performed, hardware, firmware, software, or a combination thereof performs the abort, which may include following a fallback path specified by hardware or software. And to enable testing of such a fallback path, in one implementation, hardware provides software a mechanism to always abort speculative code regions.

Apparatus and method for transactional memory and lock elision including abort and end instructions to abort or commit speculative execution

Apparatus and method for transactional memory and lock elision including an abort instruction to abort speculative execution

In one embodiment, the present invention includes a method for identifying a termination sequence for an atomic memory operation executed by a first thread, associating a timer with the first thread, and preventing the first thread from execution of a memory cluster operation after completion of the atomic memory operation until a prevention window has passed. This method may be executed by regulation logic associated with a memory execution unit of a processor, in some embodiments. Other embodiments are described and claimed.

Regulating atomic memory operations to prevent denial of service attack

In one embodiment, the present invention includes an apparatus having a first counter to count dispatches of a senior request in a memory unit, a second counter to count cycles of a processor coupled to the memory unit, and a controller coupled to the first and second counters to execute one or more one remediation measures with respect to the senior request based on a value of at least one of the counters. Other embodiments are described and claimed.

Detecting and resolving locks in a memory unit

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Portland, OR, United States of America

Prakash Math