Texas Instruments Corporation

Prakash Lakshmikanthan

Patrick David Noll

Christopher L Schutte

Madhu Sudan Ramavajjala

A method for fabricating an integrated circuit includes providing a partitioned chemical-mechanical planarization (CMP) model having a plurality of model parameters that include (i) device specific model parameters and (ii) at least one common parameter. (i) include a pre-CMP thickness of a film including a first material on an in-process device, a post-CMP target thickness for the film on the in-process device, and device group properties that account for device structure for the in-process device. (ii) includes a polish rate from an unpatterned pilot wafer having a second material thereon. The second material need not be the same as the first material. The polish time is automatically determined using the partitioned CMP model. A CMP process is performed on a patterned product wafer having a plurality of the in-process devices using a recipe including the polish time.

Run-to-run control for chemical mechanical planarization

A polishing pad for polishing a semiconductor wafer or other materials, having grooves in the polishing pad to enhance the usable lifetime of the polishing pad.

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Farmers Branch, TX, United States of America

Prakash Lakshmikanthan