Cadence Design Systems, Inc.

Prakash Kumar Lenka

Vinod Kumar

Jitendra Kumar Yadav

Hari Anand Ravi

Harsh Anil Shakrani

Rajashekhar Krishnamurthy Rao

Sumit Gupta

Virvasav Sinha

Embodiments included herein are directed towards a ring voltage-controlled oscillator based phase locked loop circuit. Embodiments may include an integral path including a plurality of resistors and a plurality of transistors configured to correct low frequency variations and a proportional path in electrical communication with the integral path, the proportional path including a plurality of transistors and a source degeneration circuit. Embodiments may further include a decoupling capacitor located at a ring voltage-controlled oscillator node in electrical communication with the proportional path, wherein the source degeneration circuit operates to cancel any effect from the ring voltage-controlled oscillator node.

Ring voltage controlled oscillator-based phase locked loop with dual charge pump architecture

The present disclosure describes a circuit that may include a first amplifier portion configured to receive a first input signal corresponding to a first clock signal and a second input signal corresponding to a second clock signal. The circuit may include a first amplifier of the first amplifier portion. The first amplifier may be configured to receive a first amplifier input signal and a second amplifier input signal. The circuit may include a second amplifier portion configured to receive a first output signal from the first amplifier portion. In a first mode, the first amplifier input signal may be based upon the second input signal and the second amplifier input signal may be based upon the first input signal. In a second mode, the first amplifier input signal may be based upon the first input signal and the second amplifier input signal may be based upon the second input signal.

Clock duty cycle measurement

Embodiments included herein are directed towards a voltage-temperature drift resistant and power efficient clock distribution circuit. Embodiments may include a current generator and a voltage generator configured to receive an input from the current generator. Embodiments may also include a regulator which may be configured to receive a reference voltage from the voltage generator as an input and to generate regulated voltage as output. The clock distribution path may operate on a regulated voltage, the regulated voltage having a value proportional to a threshold value associated with a plurality of devices included in the clock distribution path.

Clock distribution architecture

The embodiments described herein provide for methods and systems for removing power supply induced jitter from a Phase Lock Loop to provide a Power Supply Induced jitter-free clock signal to a system-on-a-chip and GDDR6 DRAM interface. In operation, a circuit reduces a DC offset between a reference voltage and a voltage regulator output to identify low frequency noise on the voltage regulator output to apply as negative feedback to reduce the low frequency noise on the voltage regulator output. The bandwidth of the circuit is increased to detect high frequency noise, which is applied as negative feedback on the voltage regulator output. Very high frequency noise is then detected and applied as negative feedback to the voltage regulator output. The circuit outputs a regulated output equal to the reference voltage and immune to the low, high, and very high frequency noise of power delivery network supply to the regulator.

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Orissa, India

Prakash Kumar Lenka