Intel Corporation

Pragyansri Pathi

Jack T Kavalieros

Robert S Chau

Gilbert W Dewey

Matthew V Metz

Sansaptak W Dasgupta

Niloy Mukherjee

Benjamin Chu-Kung

Seung Hoon Sung

Michael L Hattendorf

Sanaz Kabehie Gardner

Annalisa Cappellani

Niti Goel

Bruce E Beattie

Abhijit Jayant Pethe

James M Powers

Michael Harper

Trenches (and processes for forming the trenches) are provided that reduce or prevent crystaline defects in selective epitaxial growth of type III-V or Germanium (Ge) material (e.g., a 'buffer' material) from a top surface of a substrate material. The defects may result from collision of selective epitaxial sidewall growth with oxide trench sidewalls. Such trenches include (1) a trench having sloped sidewalls at an angle of between 40 degrees and 70 degrees (e.g., such as 55 degrees) with respect to a substrate surface; and/or (2) a combined trench having an upper trench over and surrounding the opening of a lower trench (e.g., the lower trench may have the sloped sidewalls, short vertical walls, or tall vertical walls). These trenches reduce or prevent defects in the epitaxial sidewall growth where the growth touches or grows against vertical sidewalls of a trench it is grown in.

Methods and structures to prevent sidewall defects during selective epitaxy

Techniques related to integrated circuits having MOSFETs with an unrecessed field insulator and thinner electrodes over the field insulator of ICs, systems incorporating such integrated circuits, and methods for forming them are discussed.

Trigate transistor structure with unrecessed field insulator and thinner electrodes over the field insulator

Three-dimensional germanium-based semiconductor devices formed on globally or locally isolated substrates are described. For example, a semiconductor device includes a semiconductor substrate. An insulating structure is disposed above the semiconductor substrate. A three-dimensional germanium-containing body is disposed on a semiconductor release layer disposed on the insulating structure. The three-dimensional germanium-containing body includes a channel region and source/drain regions on either side of the channel region. The semiconductor release layer is under the source/drain regions but not under the channel region. The semiconductor release layer is composed of a semiconductor material different from the three-dimensional germanium-containing body. A gate electrode stack surrounds the channel region with a portion disposed on the insulating structure and laterally adjacent to the semiconductor release layer.

Three-dimensional germanium-based semiconductor devices formed on globally or locally isolated substrates

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Portland, OR, United States of America

Pragyansri Pathi