Mentor Graphics Corporation

Pradish Mathews

Henry Potts

Ajit Singh

Srinivas Mandavilli

Rajeev Sehgal

This application discloses a computing system implementing tools and mechanisms that can incorporate a validation system into a circuit design. The validation system can be configured to monitor at least a portion of an electronic device described in the circuit design. The tools and mechanisms can identify one or more trace signals associated with the electronic device to route to the validation system, and identify one or more trigger signals associated with the electronic device to route to the validation system. The tools and mechanisms can configure the validation system to detect a conditional event corresponding a state of the one or more trigger signals, and to transmit the trace signals associated with the electronic device for debugging in response to the detected conditional event.

Streaming, at-speed debug and validation architecture

This application discloses a system to detect meta-stable glitches in a signal, such as an output of latch or other storage element. The system can include a sampling circuit configured to sample an output of a storage element. The system can include a mono-shot circuit configured to monitor the output of the storage element and generate a pulse when the monitored output of the storage element differs from the sampled output. The system can include a drive circuit configured to generate a glitch signal based, at least in part, on the sampled output, and to output the glitch signal in response to the pulse from the mono-shot circuit. The system can include an error detection circuit configured to receive the sampled output from the sampling circuit and the glitch signal from the drive circuit, and to generate an error signal when the sampled output differs from the glitch signal.

Growing community of inventors

Noida, India

Pradish Mathews