Agere Systems Guardian Corp.

Lucent Technologies Inc.

Agere Systems Inc.

Nexplanar Corporation

At&t Bell Laboratories

At+t Corp.

American Telephone & Telegraph Co., At&t Bell Laboratories

Other

Tokyo Electron Limited

Massachusetts Institute of Technology

Cabot Microelectronics Corporation

Neopad Technologies Corporation

Pradip Kumar Roy

Sailesh Mansinh Merchant

Sudhanshu Misra

Yi Ma

Sundar Srinivasan Chetlur

Hem M Vaidya

Isik C Kizilyalli

David Charles Brady

Manish Deopura

Nace Layadi

Sidhartha Sen

Carlos M Chacon

Sailesh Chittipeddi

Arun Kumar Nanda

Samir Chaudhry

Seungmoo Choi

Yuanning Chen

Richard William Gregor

Larry Bruce Fritzinger

Glenn B Alers

Siddhartha Bhowmik

Vivek Saxena

Minesh Amrat Patel

William Graham Easter

Charles Walter Pearce

Susan Clay Vitkavage

Joseph Rudolph Radosevich

Min-Liang Chen

Minseok Oh

James Theodore Clemens

Cheryl Anne Bollinger

Anthony S Oates

Edward Alan Dein

Michael A Laughery

Cletus Walter Wilkins, Jr

Jonathan Z-n Zhou

Sundar Srinivasaan Chetlur

Lionel Cooper Kimerling

Simon John Molloy

Anthony Dip

Chun-Ting Liu

Sanjeev Kaushal

Anuradha Murthy Agarwal

Taeho Kook

George K Celler

Ashok K Sinha

Daniel Knight Sparacin

Raymond Joe

Seungho Oh

Allen John Leith

Steven J Hillenius

Kin Ping Cheung

Gregg Sumio Higashi

Lee E Trimble

Ankineedu Velaga

Edward P Martin, Jr

Donald G Schimmel

William M Moller

Konstantin K Bourdelle

Kevin Yun-kang Wu

Jennifer M McKinley

Damon K DeBusk

Joseph R Radosevich

Richard A Powell

Johathan Z Zhou

Raymond H Doklan

Scott F Shive

Jonathan Zhong-Ning Zhou

Brian E Harding

Jaseph R Radosevich

Nancy Xianghong Zhao

Isik C Kizilayalli

Sidharta Sen

The present application relates to polishing pads for chemical mechanical planarization (CMP) of substrates, and methods of fabrication and use thereof. The pads described in this invention are customized to polishing specifications where specifications include (but not limited to) to the material being polished, chip design and architecture, chip density and pattern density, equipment platform and type of slurry used. These pads can be designed with a specialized polymeric nano-structure with a long or short range order which allows for molecular level tuning achieving superior thermo-mechanical characteristics. More particularly, the pads can be designed and fabricated so that there is both uniform and nonuniform spatial distribution of chemical and physical properties within the pads. In addition, these pads can be designed to tune the coefficient of friction by surface engineering, through the addition of solid lubricants, and creating low shear integral pads having multiple layers of polymeric material which form an interface parallel to the polishing surface. The pads can also have controlled porosity, embedded abrasive, novel grooves on the polishing surface, for slurry transport, which are produced in situ, and a transparent region for endpoint detection.

Customized polishing pads for CMP and methods of fabrication and use thereof

The present application relates to polishing pads for chemical mechanical planarization (CMP) of substrates, and methods of fabrication and use thereof. The pads described in this invention are customized to polishing specifications where specifications include (but not limited to) to the material being polished, chip design and architecture, chip density and pattern density, equipment platform and type of slurry used. These pads can be designed with a specialized polymeric nano-structure with a long or short range order which allows for molecular level tuning achieving superior themo-mechanical characteristics. More particularly, the pads can be designed and fabricated so that there is both uniform and nonuniform spatial distribution of chemical and physical properties within the pads. In addition, these pads can be designed to tune the coefficient of friction by surface engineering, through the addition of solid lubricants, and creating low shear integral pads having multiple layers of polymeric material which form an interface parallel to the polishing surface. The pads can also have controlled porosity, embedded abrasive, novel grooves on the polishing surface, for slurry transport, which are produced in situ, and a transparent region for endpoint detection.

Methods for producing in-situ grooves in CMP pads are provided. In general, the methods for producing in-situ grooves comprise the steps of patterning a silicone lining, placing the silicone lining in, or on, a mold, adding CMP pad material to the silicone lining, and allowing the CMP pad to solidify. CMP pads comprising novel groove designs are also described. For example, described here are CMP pads comprising concentric circular grooves and axially curved grooves, reverse logarithmic grooves, overlapping circular grooves, lassajous groves, double spiral grooves, and multiply overlapping axially curved grooves. The CMP pads may be made from polyurethane, and the grooves produced therein may be made by a method from the group consisting of silicone lining, laser writing, water jet cutting, 3-D printing, thermoforming, vacuum forming, micro-contact printing, hot stamping, and mixtures thereof.

Methods for producing in-situ grooves in chemical mechanical planarization (CMP) pads, and novel CMP pad designs

A polishing pad for chemical mechanical planarization of a film on a substrate is customized by obtaining one or more characteristics of a structure on a substrate. For example, when the structure is a chip formed on a semiconductor wafer, the one or more characteristics of the structure can include chip size, pattern density, chip architecture, film material, film topography, and the like. Based on the one or more characteristics of the structure, a value for the one or more chemical or physical properties of the pad is selected. For example, the one or more chemical or physical properties of the pad can include pad material hardness, thickness, surface grooving, pore size, porosity, Youngs modulus, compressibility, asperity, and the like.

Customized polish pads for chemical mechanical planarization

Methods for producing in-situ grooves in CMP pads are provided. In general, the methods for producing in-situ grooves comprise the steps of patterning a silicone lining, placing the silicone lining in, or on, a mold, adding CMP pad material to the silicone lining, and allowing the CMP pad to solidify. CMP pads comprising novel groove designs are also described. For example, described here are CMP pads comprising concentric circular grooves and axially curved grooves, reverse logarithmic grooves, overlapping circular grooves, lassajous grooves, double spiral grooves, and multiple overlapping axially curved grooves. The CMP pads may be made from polyurethane, and the grooves produced therein may be made by a method from the group consisting of silicone lining, laser writing, water jet cutting, 3-D printing, thermoforming, vacuum forming, micro-contact printing, hot stamping, and mixtures thereof.

The invention provides a waveguide with a waveguide core having longitudinal sidewall surfaces, a longitudinal top surface, and a longitudinal bottom surface that is disposed on a substrate. An interface layer is disposed on at least one longitudinal sidewall surface of the waveguide core. A waveguide cladding layer is disposed on at least the waveguide core sidewall and top surfaces, over the interface layer. The waveguide of the invention can be produced by forming a waveguide undercladding layer on a substrate, and then forming a waveguide core on the undercladding layer. An interface layer is then formed on at least a longitudinal sidewall surface of the waveguide core, and an upper cladding layer is formed on a longitudinal top surface and on longitudinal sidewall surfaces of the waveguide core, over the interface layer.

Microphotonic waveguide including core/cladding interface layer

A method for using a silicon germanium (SiGe) surface layer to integrate a high-k dielectric layer into a semiconductor device. The method forms a SiGe surface layer on a substrate and deposits a high-k dielectric layer on the SiGe surface layer. An oxide layer, located between the high-k dielectric layer and an unreacted portion of the SiGe surface layer, is formed during one or both of deposition of the high-k dielectric layer and an annealing process after deposition of the high-k dielectric layer. The method further includes forming an electrode layer on the high-k dielectric layer.

Silicon germanium surface layer for high-k dielectric integration

A method of manufacture for semiconductor electronic products and a circuit structure. A semiconductor material has a surface region and dopant is provided to a portion of the surface region. The portion of the surface region provided with the dopant is irradiated with sufficient energy to induce diffusion of the dopant from the portion of the surface region to another region of the semiconductor material. A method for manufacturing an electronic product with a semiconductor material having a surface and two spaced-apart regions along the surface for receiving dopant includes forming a field effect transistor gate structure is along the surface and over a third region of the surface between the two spaced-apart regions. Dopant is provided to the spaced-apart regions which are heated to a temperature at least 50 degrees C. higher than the peak temperature which results in the third region when the spaced-apart regions are heated. A circuit comprises a semiconductor material having a surface region for formation of devices, a field effect transistor gate structure formed on the surface region, the gate structure including a conductive layer and an amorphous insulative layer having a dielectric constant greater than five relative to free space. The insulative layer is formed between the conductive layer and the surface region. A source region is formed along the surface region and a drain region is also formed along the surface region. The gate structure, source region and drain region are configured to form an operable field effect transistor.

Selective laser annealing of semiconductor material

A method for forming an oxide layer on a vertical, non-planar semiconductor surface provides a low stress oxide layer having a pristine interface characterized by a roughness of less than 3 angstroms. The oxide layer includes a portion that is substantially amorphous and notably dense. The oxide layer is a graded growth oxide layer including a composite of a first oxide portion formed at a relatively low temperature below the viscoelastic temperature of the oxide film and a second oxide portion formed at a relatively high temperature above the viscoelastic temperature of the oxide film. The process for forming the oxide layer includes thermally oxidizing at a first temperature below the viscoelastic temperature of the film, and slowly ramping up the temperature to a second temperature above the viscoelastic temperature of the film and heating at the second temperature. After the second, high temperature oxidation above the viscoelastic temperature, the structure is then slowly cooled under gradual, modulated cooling conditions.

Method and structure for graded gate oxides on vertical and non-planar surfaces

Growing community of inventors

Orlando, FL, United States of America

Pradip Kumar Roy