Xilinx, Inc.

Pradip Kar

Nithin Kumar Guggilla

Bing Tian

Chaithanya Dudha

Satyaprakash Pareek

Stephen P Rozum

Shangzhi Sun

Ryan Linderman

Michael Keilson

Implementing a hardware description language (HDL) memory includes determining, using computer hardware, a width and a depth of the HDL memory specified as an HDL module for implementation in an integrated circuit (IC), partitioning, using the computer hardware, the HDL memory into a plurality of super slices corresponding to columns and the plurality of super slices into a plurality of super tiles arranged in rows. A heterogeneous memory array may be generated, using the computer hardware. The heterogeneous memory array is formed of different types of memory primitives of the IC. Input and output circuitry configured to access the heterogeneous memory array can be generated using the computer hardware.

Implementing a hardware description language memory using heterogeneous memory primitives

Implementing an asymmetric memory having random port ratios using memory primitives can include detecting, using computer hardware, a hardware description language (HDL) random access memory (RAM) within a circuit design. The HDL RAM is asymmetric. Using computer hardware, a number of a plurality of memory primitives needed to implement the HDL RAM as a RAM circuit are determined based on a maximum port width ratio of the memory primitives defined as 1:N and a port width ratio of the HDL RAM defined as 1:M, wherein each of M and N is an integer and a power of two and M exceeds N. The RAM circuit is asymmetric. Using the computer hardware, a write circuit and/or a read circuit can be generated for a first port of the RAM circuit. Further, using the computer hardware, a write circuit and/or a read circuit can be generated for a second port of the RAM circuit.

Implementing an asymmetric memory with random port ratios using dedicated memory primitives

Embodiments herein describe techniques for designing a compressed hardware implementation of a user-designed memory. In one example, a user defines a memory in hardware description language (HDL) with a depth (D) and a width (W). To compress the memory, a synthesizer designs a core memory array representing the user-defined memory. Using addresses, the synthesizer can identify groups of nodes in the array that can be compressed into a memory element. The synthesizer designs input circuitry such as a data replicator and a write enable generator for generating the inputs and control signals for the groups. The synthesizer can then implement the design in an integrated circuit where each group of nodes maps to a single memory element, thereby resulting in a compressed design.

Multi dimensional memory compression using bytewide write enable

Disclosed approaches of pipelining cascaded memory blocks include determining memory blocks combined to implement a memory in a netlist of a circuit design. A model of the memory blocks arranged in a matrix is generated and a total number of delay registers that can be inserted between an input and an output of the memory is determined based on an input latency constraint. For each column, positions of delay registers are determined between an input of the column and the output of the memory. The circuit design is modified to include the delay registers at the determined positions.

Automatic pipelining of memory circuits

Modifying initialization data for a memory array of a circuit design can include providing, using a processor, portions of an incoming stream of data for initializing the memory array to emulation objects of a memory array emulator. The memory array emulator is configured to emulate an implementation of the memory array and the emulation objects represent block random access memories (block RAMs) of the memory array. Using the processor, the data can be formatted using the emulation objects to generate initialization data, wherein the data is formatted based upon configuration settings of the block RAMs emulated by the respective emulation objects. A configuration bitstream can be updated, using the processor, with the initialization data.

Growing community of inventors

San Jose, CA, United States of America

Pradip Kar