Xilinx, Inc.

Pradip Jha

Dinesh K Monga

Paul R Schumacher

David A Knol

Sudipto Chakraborty

David Bruce Parlour

Ian D Miller

Jorn W Janneck

Stephen P Rozum

Brendan Matthew O'Higgins

Alec J Wong

Steven Banks

Sonal Santan

Vinod Kumar Kathail

Qin Qiong Zhang

Shail Aditya Gupta

Dinesh D Gaitonde

Bart Reynolds

Ravi Nagarajarao Kurlagunda

Henry E Styles

Alan M Frost

Fernando J Martinez Vallina

Vishal Suthar

Yau-Tsun Steven Li

Nicholas A Mezei

Atul Srinivasan

Sheng Zhou

Srinivas Beeravolu

Vidhumouli Hunsigida

Bin Ochotta

Ryan Linderman

Jeffrey M Fifield

Smitha Sundaresan

Dennis McCrohan

Bennet An

Siddarth Rele

A unified data model for creating a circuit design for a heterogeneous integrated circuit is provided. The unified data model is stored as a data structure in computer hardware. The unified data model includes a unified netlist specifying the circuit design and a unified device model representing the heterogeneous integrated circuit. The unified netlist includes netlist objects configured to communicate over bitwise connections and network connections representing packet-based communications. The unified netlist may be mapped to the unified device model using computer hardware. Using the computer hardware, at least a portion of the device model may be displayed in coordination with at least a portion of the unified netlist mapped thereto.

Unified data model for heterogeneous integrated circuit

For an application specifying a software portion for implementation within a data processing engine (DPE) array of a device and a hardware portion for implementation within programmable logic (PL) of the device, a logical architecture for the application and a first interface solution specifying a mapping of logical resources to hardware of an interface circuit block between the DPE array and the programmable logic are generated. A block diagram of the hardware portion is built based on the logical architecture and the first interface solution. An implementation flow is performed on the block diagram. The software portion of the application is compiled for implementation in one or more DPEs of the DPE array.

Hardware-software design flow for heterogeneous and programmable devices

High level synthesis for a circuit design may include detecting, using a processor, an encrypted, high level programming language (HLL) core for inclusion in a circuit design, decrypting, using the processor, the encrypted HLL core into volatile memory, and generating, using the processor, an encrypted, intermediate representation (IR) of the circuit design including an encrypted IR of the HLL core. An encrypted hardware description language (HDL) circuit design may be generated, using the processor, from the encrypted IR of the circuit design. The encrypted HDL circuit design includes an encrypted HDL core that is functionally equivalent to the encrypted HLL core.

High level programming language core protection for high level synthesis

Methods and systems are disclosed for placement and routing of a circuit design. A set of timing constraints is retrieved that specifies timing for objects included in a first shell circuit design configured to provide an interface for communication between the circuit design and the set of dedicated hardware resources on an IC. One or more objects of the first shell circuit design that do not affect timing of the circuit design are identified and removed from the first shell circuit design to produce a second shell circuit design. The circuit design is placed and routed according to timing constraints specified for objects of the first shell circuit design that are included in the second shell circuit design. The placed and routed circuit design is stored in a memory circuit.

Method and apparatus for placement and routing of circuit designs

Message filtering may include, during a first processing phase of a design specified in source code, creating a filter table including message filters and storing the filter table in a memory using a processor. Each message filter may specify a message criterion and an object identifier of the design. During a subsequent processing phase of the design, received messages may be compared with the message filters of the filter table using the processor. Responsive to determining that a selected message matches a message criterion and an object identifier of a selected message filter, the message may be suppressed using the processor.

Message filtering for electronic design automation systems

A software development-based compilation flow for circuit design may include executing, using a processor, a makefile including a plurality of rules for hardware implementation. Responsive to executing a first rule of the plurality of rules, a source file including a kernel specified in a high level programming language may be selected; and, an intermediate file specifying a register transfer level implementation of the kernel may be generated using the processor. Responsive to executing a second rule of the plurality of rules, a configuration bitstream for a target integrated circuit may be generated from the intermediate file using the processor. The configuration bitstream includes a compute unit circuit implementation of the kernel.

Software development-based compilation flow for hardware implementation

Constraint handling for a circuit design may include determining, using a processor, instances of parameterizable modules of a circuit design associated with constraints based upon a predefined hardware description language attribute within the instances, extracting, using the processor, parameter values from the instances of the parameterizable modules, and generating, using the processor, static constraint files for the instances of the parameterizable modules using the extracted parameter values.

Constraint handling for parameterizable hardware description language

A method of generating data for estimating resource requirements for a circuit design is disclosed. The method comprises identifying a plurality of intermediate circuit modules of netlists for circuit designs; elaborating each intermediate circuit module of the plurality of intermediate circuit modules according to an associated plurality of parameter sets; generating an estimate of resources for each intermediate circuit module and parameter set of the associated plurality of parameter sets; and storing the estimates of resources for the intermediate circuit modules.

Method of generating data for estimating resource requirements for a circuit design

A method is provided for exporting design constraints from a circuit design. In response to a first user command indicating a design constraint and a pattern, the design constraint is assigned to each object in the circuit design that matches the pattern, and the pattern is stored in a database. In response to a second user command to export design constraints of the circuit design, for each design constraint assigned to a respective set of objects of the circuit design, a pattern stored in the database that matches the respective set of the objects is determined and the design constraint is added to an export file in a format that uses the determined pattern. Design constraints on individual ones of the set of the objects indicated by the determined pattern are omitted from the export file.

System and method for import and export of design constraints

Approaches for estimating power consumption of a circuit from a circuit design. According to one embodiment, a representation of the circuit design specifies a plurality of circuit elements for implementing the circuit design. The circuit elements are matched to structural templates. Each structural template is representative of one or more circuit elements and has associated information descriptive of one or more toggle rates. Respective estimated toggle rates are determined for the circuit elements of the circuit design based on the information descriptive of one or more toggle rates associated with the matched structural templates. An estimated power consumption level is determined as a function of the estimated toggle rates of the circuit elements, and data indicative of the estimated power consumption level is output.

Power estimation of a circuit design

A method of estimating resource requirements for a circuit design is disclosed. The method comprises identifying intermediate circuit modules of a netlist associated with the circuit design; accessing a library of resource requirements for intermediate circuit modules of netlists for circuit designs; selecting intermediate circuit modules of the library according to predetermined parameters for the circuit design; and generating an estimate of resource requirements for the circuit design based upon resource requirements of the selected intermediate circuit modules.

Method of estimating resource requirements for a circuit design

Approaches for determining a static timing analysis of a logic design are disclosed. Physical delay arcs of a plurality of physical elements of an integrated circuit specify respective propagation delays from inputs of the physical elements to outputs of the physical elements. Logic components of the logic design are mapped to selected ones of the physical components of the physical elements. For each of the logic components, the logic delay arcs are determined from the physical delay arcs. Each logic delay arc for each logic component specifies a propagation delay from an input of the logic component to an output of the logic component. A static timing analysis of the logic components is performed using the logic delay arc, and data from the timing analysis is output.

Timing analysis of a mapped logic design using physical delays

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Cupertino, CA, United States of America

Pradip Jha