International Business Machines Corporation

Globalfoundries Inc.

Pradip Bose

Alper Buyuktosunoglu

Hans Mikael Jacobson

Augusto Javier Vega

Jude A Rivers

Victor V Zyuban

Karthik V Swaminathan

Chen-Yong Cher

Prabhakar Nandavar Kudva

Ramon Bertran Monfort

Ramon M Bertran

Hubertus Franke

Michael Stephen Floyd

Vijayalakshmi Srinivasan

Jeonghee Shin

Schuyler Eldridge

Ravi Nair

Phillip John Restle

Stanley Everett Schuster

Peter William Cook

Timothy John Slegel

Eren Kursun

Christos Vezyrtzis

Pierce I-Jen Chuang

Hillery C Hunter

Zhigang Hu

Xiaochen Guo

Augusto J Vega

Philip George Emma

John-David Wellman

Swagath Venkataramani

Moinuddin K Qureshi

Jingwen Leng

Dilma Menezes Da Silva

John A Darringer

Yazhou Zu

Priyanka Tembey

Timothy Joseph Chainer

Balaram Sinharoy

Pritish Ranjan Parida

Giora Biran

Bruce Martin Fleischer

Thomas Winters Fox

Srinivasan Ramani

Tobias Webel

Vaidyanathan Srinivasan

Preetham M Lobo

Michael K Gschwind

Rajiv V Joshi

Hung Qui Le

Alan G Gara

Malcolm Scott Ware

Richard James Eickemeyer

Ken Van Vu

Bruce Joseph Ronchetti

Bryan Savoye Rosenburg

Robert Matthew Senger

Kyung D Ryu

Jayanta Basak

Tejas S Karkhanis

Maria Lorena Pesantez

Dung Q Nguyen

Hendrik F Hamann

Robert K Montoye

Karthick Rajamani

Bulent Abali

Michele M Franceschini

Gary Dale Carpenter

Jeffrey Haskell Derby

K Paul Muller

Susan Elizabeth Eisen

Lee Evan Eisen

Xiaoqiao Meng

Gregory Scott Still

Canturk Isci

Emrah Acar

Todd Jon Rosedahl

David Scott Ray

Seongwon Kim

Daniel Arthur Prener

Francis Patrick O'Connell

Miles Robert Dooley

Bishop Chapman Brock

Heather Lynn Hanson

Alan Weger

Christopher J Gonzalez

Robert Alan Philhower

John Barry Griswell, Jr

Timothy J Siegel

Eli Arbel

Raymond Cheung Yeung

Jeffrey Richard Summers

David H Albonesi

Ruhi Sarikaya

Pia Naoko Sanda

Kin Shing Chan

Shiri Moran

Michael R Scheuermann

Wolfram Sauer

Prashant Jayaprakash Nair

Embodiments for providing enhanced location-aware protection of latches in a computing environment are provided. One or more latches are combined in one or more of a plurality of bounding boxes on a two-dimensional circuit design layout based on one or more rules. A location-aware interleaving of error correction codes ('ECC') and burst error correction codes may be selectively applied to one or more latches in those of the plurality of bounding boxes, where multiple bit errors are corrected.

Location-aware protection system of latches (LAPS-L)

In a first device, a local classification and a local classification confidence score corresponding to an event input are computed. At the first device in response to a broadcast request, a remote classification and a remote classification confidence score corresponding to the event input are received, the remote classification and the remote classification confidence score being computed at a second device. At the first device, a consensus classification including the most frequent classification from a set of all received remote classifications and the local classification is formed, provided the number of classifications including the most frequent classification exceeds a threshold. In response to a consensus classification confidence score corresponding to the consensus classification exceeding a confidence threshold, a local classification model is updated. Based on the local classification and the consensus classification, the event input is assigned to a classification.

Adaptive multi-agent cooperative computation and inference

Tasks of directed acyclic graphs (DAGs) may be dynamically scheduled based on a plurality of constraints and conditions, task prioritization policies, task execution estimates, and configurations of a heterogenous system. A machine learning component may be initialized to dynamically schedule the tasks of the DAGs.

Learning agent based application scheduling

A system includes a determination component that determines output for successively larger neural networks of a set; and a consensus component that determines consensus between a first neural network and a second neural network of the set. A linear chain of increasingly complex neural networks trained on progressively larger inputs is utilized (e.g., increasingly complex neural networks is generally representative of increased accuracy). Outputs of progressively networks are computed until a consensus point is reached&#x2014;where two or more successive large networks yield a same inference output. At such point of consensus the larger neural network of the set reaching consensus can be deemed appropriately sized (or of sufficient complexity) for a classification task at hand.

System and method for consensus-based representation and error checking for neural networks

Described are techniques for scheduling tasks on a heterogeneous system on a chip (SoC). The techniques including receiving a directed acyclic graph at a meta pre-processor associated with a heterogeneous system-on-chip and communicatively coupled to a scheduler, where the directed acyclic graph corresponds to a control flow graph of respective tasks associated with an application executed by the heterogeneous system-on-chip. The techniques further including determining, using a learning agent implementing machine learning algorithms, a rank for a respective task in the directed acyclic graph, wherein the learning agent receives as input the directed acyclic graph, constraints associated with the directed acyclic graph, and heuristics regarding previously completed tasks. The techniques further including providing the respective task to the scheduler for execution on the heterogeneous system-on-chip according to the rank.

Heterogeneous system on a chip scheduler with learning agent

Systems, computer-implemented methods and/or computer program products that facilitate management of resources are provided. In one embodiment, a computer-implemented method comprises: employing, by a system operatively coupled to a processor, at least one model to predict respective token needs by a set of processing elements during execution of a workload; and exchanging, by the system, one or more tokens between a subset of the processing elements as a function of the predicted token needs.

Swarm-based resource management

A computer-implemented method, a computer system and a computer program product customize generation and application of stress test conditions in a processor core. The method includes receiving a workload at the processor core, where the workload includes a plurality of instructions and the processor core comprises a plurality of macros. The method also includes obtaining macro performance data for each macro in the plurality of macros from the processor core. The method further includes determining a switching activity level for each macro in the plurality of macros when each instruction in the plurality of instructions is run based on the macro performance data. Lastly, the method includes generating a stressmark comprising the plurality of instructions in the workload, where the stressmark is associated with a macro in the plurality of macros when the switching activity level for the macro is above a minimum threshold.

Customizing stressmarks in a computer system

Described are techniques for scheduling tasks on a heterogeneous system on a chip (SoC). The techniques including receiving a directed acyclic graph at a meta pre-processor associated with a heterogeneous SoC and communicatively coupled to a scheduler, wherein the directed acyclic graph corresponds to a control flow graph of tasks associated with an application executed by the heterogeneous SoC. The techniques further including determining a rank for a respective task in the directed acyclic graph, wherein the rank is based on a priority of the respective task and a slack in the directed acyclic graph. The techniques further including providing the respective task to the scheduler for execution on the heterogeneous SoC according to the rank.

Heterogeneous system on a chip scheduler

Techniques facilitating voltage droop reduction and/or mitigation in a processor core are provided. In one example, a system can comprise a memory that stores, and a processor that executes, computer executable components. The computer executable components can comprise an observation component that detects one or more events at a first stage of a processor pipeline. An event of the one or more events can be a defined event determined to increase a level of power consumed during a second stage of the processor pipeline. The computer executable components can also comprise an instruction component that applies a voltage droop mitigation countermeasure prior to the increase of the level of power consumed during the second stage of the processor pipeline and a feedback component that provides a notification to the instruction component that indicates a success or a failure of a result of the voltage droop mitigation countermeasure.

Proactive voltage droop reduction and/or mitigation in a processor core

Techniques facilitating determination and correction of physical circuit event related errors of a hardware design are provided. A system can comprise a memory that stores computer executable components and a processor that executes computer executable components stored in the memory. The computer executable components can comprise a simulation component that injects a fault into a latch and a combination of logic of an emulated hardware design. The fault can be a biased fault injection that can mimic an error caused by a physical circuit event error vulnerability. The computer executable components can also comprise an observation component that determines one or more paths of the emulated hardware design that are vulnerable to physical circuit event related errors based on the biased fault injection.

Determination and correction of physical circuit event related errors of a hardware design

Various embodiments are provided for load balancing of machine learning operations in a computing environment by a processor. One or more machine learning operations performing inference or training operations may by dynamically balanced between one or more edge computing devices in a wireless communication network and a cloud computing system for increasing performance of a selected metric.

Power efficient machine learning in cloud-backed mobile systems

An N modular redundancy method, system, and computer program product include a computer-implemented N modular redundancy method for neural networks, the method including selectively replicating the neural network by employing one of checker neural networks and selective N modular redundancy (N-MR) applied only to critical computations.

Reducing the cost of n modular redundancy for neural networks

Techniques facilitating voltage management via on-chip sensors are provided. In one example, a computer-implemented method can comprise measuring, by a first processor core, power supply information. The computer-implemented method can also comprise measuring, by the first processor core, a value of an electrical current generated by the first processor core. Further, the computer-implemented method can comprise applying, by the first processor core, a mitigation technique at the first processor core in response to a determination that a combination of the power supply noise information and the value of the electrical current indicates a presence of a voltage noise at the first processor core.

On-chip supply noise voltage reduction or mitigation using local detection loops

A computer-implemented method optimizes a neural network. One or more processors define layers in a neural network based on neuron locations relative to incoming initial inputs and original outgoing final outputs of the neural network, where a first defined layer is closer to the incoming initial inputs than a second defined layer, and where the second defined layer is closer to the original outgoing final outputs than the first defined layer. The processor(s) define parameter criticalities for parameter weights stored in a memory used by the neural network, and associate defined layers in the neural network with different memory banks based on the parameter criticalities for the parameter weights. The processor(s) store parameter weights used by neurons in the first defined layer in the first memory bank and parameter weights used by neurons in the second defined layer in the second memory bank.

Parameter criticality-aware resilience

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Yorktown Heights, NY, United States of America

Pradip Bose