Sony Electronics Inc

Sony Corporation of Japan

Sony Corporation

Pradip Banerjee

Atul V Ghia

Patrick Chuang

Simon Lau

Robert Haig

A dynamic I/O configuration and protocol includes a configurable data bus for optimizing data throughput. The configurable data bus includes multiple bi-directional data buses between a memory device and a controller to maximize the data transfer efficiency of operation sequences and thereby optimize data throughput to and from the memory device. Each of the bi-directional data buses are configured for utilization in both read operations from and write operations to the memory device. Using control input signal lines, the controller specifies a current operation to be performed and the data bus to be used to perform the current operation. The specific instructions that are provided from the controller to the memory device depend on the particular operation sequence being performed.

Dynamic input/output: configurable data bus for optimizing data throughput

The present invention includes a central processing unit (CPU) coupled to a bus. Cache memory devices are coupled to the bus to receive memory requests from the CPU. Each of the cache memory devices includes a cache memory which is coupled to the controller circuit. The controller circuit provides control signals, which enable the cache memory to execute a memory operation requested by the CPU. The controller circuit is coupled to receive predefined address bits comprising memory addresses and memory requests issued by the CPU. Each of the controller circuits disposed in each cache memory device is further coupled to receive an identification number unique to each of the cache memory devices coupled to the bus. The controller circuits disposed in each of the cache memory devices compares the unique identification number with the predefined address bits, such that if the identification number and the predefined address bits match, the controller circuit provides control signals to enable its cache memory to execute the memory operation requested by the CPU at the cache memory location corresponding to the main memory address. In the event the identification does not match the predefined bits of the address, the memory controller circuit does not provide control signals to enable the memory to execute the memory operation and disables output driver circuits disposed within the cache.

Method and apparatus for connecting memory chips to form a cache memory

An internal clock that generates a signal from a system clock is provided. The signal generated by the internal clock has a duty cycle that is independent of the system clock. The internal clock may be tuned to provide a desired duty cycle that corresponds to the period required for an operation such as a write to memory. The internal clock may provide a duty cycle that is longer or shorter than the system clock. The signal generated by the internal clock has the same period as the signal generated by the system clock to maintain synchronization of system operations.

Duty cycle independent tunable clock

The architecture of the cache memory of the present invention includes a data RAM, a TAG RAM, a controller and pad logic on a single integrated circuit chip. The cache memory is coupled to a CPU and a memory bus controller over a host bus. The host bus receives read data from the cache memory and provides write data to the cache memory. The cache memory controller provides signals to the memory bus controller to indicate whether data accessed by the CPU resides in the cache memory. The present invention increases memory speed by allowing circuit elements in the cache memory to operate during both phases of a system clock signal.

Digital circuit for performing multicycle addressing in a digital memory

The method and apparatus of the present invention provides an interface between a testing device and a random access memory (RAM). The RAM comprises two types of RAM, a TAG RAM and a data RAM. In normal operation, the TAG RAM is not coupled to any devices external to the RAM. Thus, to test the TAG RAM, means must be provided to couple the testing device with the RAG RAM. One possible configuration for interface the TAG RAM with the testing device is to dedicate a line from the testing device to the TAG RAM for each output pin of the testing device, which significantly increases the size of the chip. To reduce this increase in size, according to the present invention, the write lines from the testing device share the bus used by the TAG RAM during normal operation. A multiplexer selects between the testing data and normal address data to insure the integrity of data over the bus. By sharing lines according to the present invention, a TAG RAM may be interfaced to a testing device with a minimum expansion of chip size.

Scheme to test/repair multiple large RAM blocks

The charge shared precharge circuit of the present invention is coupled to the match line. The precharge circuit is disposed between the match line and a match line, and includes a CMOS passgate having an N channel and a P channel gate. An inverter acts as a match driver and is coupled between the match and match lines at the CMOS passgate's input and output. The input to the N channel gate of the pass gate is coupled through an inverter to the input of the P channel gate. The N channel gate is further coupled to V.sub.cc through two serially coupled P channel transistors receive BEQ line and an SAE signal, respectively. At the beginning of a compare cycle, BEQ is driven low as is SAE, thereby turning on the serially coupled P channel transistors and coupling V.sub.cc to the input of the N channel gate of the passgate. The P channel gate of the passgate is also opened due to the placement of the inverter between the N and P channel gates. The passgate is thereby turned on and current passes through the passgate between the match and match lines. The opening of the passgate and the coupling of the inverter between the match and match lines, results in a shorting of V.sub.cc to ground. The shorting of V.sub.cc to ground results in a voltage precharge of the match line to V.sub.cc /2. After a predetermined precharge time, the SAE signal is driven high thereby turning off the P channel transistor, and electrically decoupling V.sub.cc from the gates of the CMOS passgate and the match line. The compare circuit of the present invention then compares the bits of word A with word B, as described herein.

Charge shared precharge scheme to reduce compare output delays

The present invention discloses apparatus and methods for comparing the contents of two digital words and determining whether or not they identically match. The present invention's high speed compare circuit includes a plurality of bit compare block circuits (0 through N) which are coupled in a wired OR configuration to a match line. Each of the bit compare blocks receives a single bit from a first word A to be compared to a corresponding bit in a second word B. A charge share precharge circuit is coupled to the match line for precharging the match line to a voltage level of V.sub.cc /2. A match feed back circuit is also coupled to the match line and the charge precharge circuit to improve the speed at which the match line is precharged to the voltage level of V.sub.cc /2. A latch is coupled to the match line to electrically latch the state of the match line subsequent to the comparison operation. The comparison circuit of the present invention is dynamic and retains its high speed performance characteristics independent of the word lengths being compared.

High performance dynamic compare circuit

The present invention provides methods and apparatus for resetting all of the cells in a random access memory (RAM) during one clock cycle without requiring ancillary drivers. At the start of the reset cycle, each column in the memory array is selected to receive the reset value and then each data line in the array is driven low while the inverse of the data line is driven high. After a first predetermined delay, each word line is driven high and all of the memory cells are thus reset. The word lines are then driven low and after a second predetermined delay, the data lines are driven back to a high value. In this manner, each cell in the memory array is reset during one clock cycle.

Single cycle flush for RAM memory

A high speed compare circuit includes a plurality of bit compare block circuits (0 through N) which are coupled in a wired OR configuration to a match line. Each bit compare block (0 through N) includes a compare circuit for receiving a bit and its complement from word A and a corresponding bit and its complement from word B. The compare circuit includes an output line which is normally maintained high to indicate that a match exists. The output line is coupled to a common mode dip filter which is comprised of N and P channel transistors. The output line of the compare circuit is coupled to the gates of a first and a second P channel transistor. The first P channel transistor is coupled to V.sub.cc, and the second P channel transistor is coupled in series to the first P channel transistor. The output line from the compare circuit is also coupled to the gate of an N channel transistor coupled in series with the first and second P channel transistors. The N channel transistor is also coupled to ground. A third P channel transistor is electrically coupled between the first and the second P channel transistors and to ground. A dip filter output line (referred to herein as 'compare out') is coupled between the second P channel transistor and the N channel transistor, as well as to the gate of the third P channel transistor. In operation, the common mode dip filter of the present invention filters relatively short duration voltage dips from the output of the compare circuit. These transient voltage dips may be generated through the use of, for example, sense amplifiers to sense memory locations to retrieve words to be compared by the present invention.

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San Jose, CA, United States of America

Pradip Banerjee