Kla Tencor Corporation

Kla Corporation

Kla-tencor Technologies Corporation

Pradeep Vukkadala

Jaydeep K Sinha

Sathish Veeraraghavan

Haiguang Chen

Amir Azordegan

Sergey Kamensky

Craig MacNaughton

Ady Levy

Bin-Ming Benjamin Tsai

Mark Davis Smith

Michael D Kirk

Oreste Donzella

Dieter Mueller

Prasanna Dighe

John S Graves

Guy Parsey

Cao Zhang

Anatoly Burov

Kunlun Bai

Xiaohan Li

Mehdi Vaez-Iravani

George J Kren

John Joseph Biafore

Kurt Lindsay Haller

Krishna Rao

Wei Chang

Ali Salehpour

Jiayao Zhang

Craig Higgins

Soham Dey

Jong-Hoon Kim

A mask pattern for a semiconductor device can be used as an input to determine a photoresist thickness probability distribution using a machine learning module. For example, the machine learning module can determine a probability map of Z-height. This can be used to determine stochastic variation in photoresist thickness for a semiconductor device. The Z-height may be calculated at a coordinate in the X-direction and Y-direction.

Prediction and metrology of stochastic photoresist thickness defects

A system for mask design repair may develop a simulation-based model of a layer thickness after one or more process steps for fabricating features on a sample, develop a transformed model of the fabrication process that emulates the simulation-based model and has a faster evaluation speed than the simulation-based model, and where the inputs to the transformed model include the input mask design, and where the outputs of the transformed model include one or more output parameters associated with fabrication of the input mask design as well as one or more sensitivity metrics describing sensitivities of the one or more output parameters to variations of the input mask design. The system may further receive a candidate mask design and generate a repaired mask design based on the transformed model and the candidate mask design.

Lithography mask repair by simulation of photoresist thickness evolution

Systems and methods for prediction and measurement of overlay errors are disclosed. Process-induced overlay errors may be predicted or measured utilizing film force based computational mechanics models. More specifically, information with respect to the distribution of film force is provided to a finite element (FE) model to provide more accurate point-by-point predictions in cases where complex stress patterns are present. Enhanced prediction and measurement of wafer geometry induced overlay errors are also disclosed.

Process-induced distortion prediction and feedforward and feedback correction of overlay errors

A controller is configured to perform at least a first characterization process prior to at least one discrete backside film deposition process on a semiconductor wafer; perform at least an additional characterization process following the at least one discrete backside film deposition process; determine at least one of a film force or one or more in-plane displacements for at least one discrete backside film deposited on the semiconductor wafer via the at least one discrete backside film deposition process based on the at least the first characterization process and the at least the additional characterization process; and provide at least one of the film force or the one or more in-plane displacements to at least one process tool via at least one of a feed forward loop or a feedback loop to improve performance of one or more fabrication processes.

Process-induced displacement characterization during semiconductor production

Prediction based systems and methods for optimizing wafer chucking and lithography control are disclosed. Distortions predicted to occur when a wafer is chucked by a chucking device are calculated and are utilized to control chucking parameters of the chucking device. Chucking parameters may include chucking pressures and chucking sequences. In addition, predicted distortions may also be utilized to facilitate application of anticipatory corrections. Controlling chucking parameters and/or applying anticipatory corrections help reducing or minimizing overlay errors.

Prediction based chucking and lithography control optimization

Wafer geometry measurement tools and methods for providing improved wafer geometry measurements are disclosed. Wafer front side, backside and flatness measurements are taken into consideration for semiconductor process control. The measurement tools and methods in accordance with embodiments of the present disclosure are suitable for handling any types of wafers, including patterned wafers, without the shortcomings of conventional metrology systems.

Patterned wafer geometry measurements for semiconductor process controls

Systems and methods for improving results of wafer higher order shape (HOS) characterization and wafer classification are disclosed. The systems and methods in accordance with the present disclosure are based on localized shapes. A wafer map is partitioned into a plurality of measurement sites to improve the completeness of wafer shape representation. Various site based HOS metric values may be calculated for wafer characterization and/or classification purposes, and may also be utilized as control input for a downstream application. In addition, polar grid partitioning schemes are provided. Such polar grid partitioning schemes may be utilized to partition a wafer surface into measurement sites having uniform site areas while providing good wafer edge region coverage.

Systems, methods and metrics for wafer high order shape characterization and wafer classification using wafer dimensional geometry tool

The present invention may include acquiring a wafer shape value at a plurality of points of a wafer surface at a first and second process level, generating a wafer shape change value at each of the points, generating a set of slope of shape change values at each of the points, calculating a set of process tool correctables utilizing the generated set of slope of shape change values, generating a set of slope shape change residuals (SSCRs) by calculating a slope of shape change residual value at each of the points utilizing the set of process tool correctables, defining a plurality of metric analysis regions distributed across the surface, and then generating one or more residual slope shape change metrics for each metric analysis region based on one or more SSCRs within each metric analysis region.

Overlay and semiconductor process control using a wafer geometry metric

Systems and methods for prediction of in-plane distortions (IPD) due to wafer shape in semiconductor wafer chucking process is disclosed. A series of Zernike basis wafer shapes process to emulate the non-linear finite element (FE) contact mechanics model based IPD prediction is utilized in accordance with one embodiment of the present disclosure. The emulated FE model based prediction process is substantially more efficient and provides accuracy comparable to the FE model based IPD prediction that utilizes full-scale 3-D wafer and chuck geometry information and requires computation intensive simulations. Furthermore, an enhanced HOS IPD/OPD prediction process based on a series of Zernike basis wafer shape images is also disclosed.

System and method to emulate finite element model based prediction of in-plane distortions due to semiconductor wafer chucking

Systems and methods to detect, quantify, and control process-induced asymmetric signatures using patterned wafer geometry measurements are disclosed. The system may include a geometry measurement tool configured to obtain a first set of wafer geometry measurements of the wafer prior to the wafer undergoing a fabrication process and to obtain a second set of wafer geometry measurements of the wafer after the fabrication process. The system may also include a processor in communication with the geometry measurement tool. The processor may be configured to: calculate a geometry-change map based on the first set of wafer geometry measurements and the second set of wafer geometry measurements; analyze the geometry-change map to detect an asymmetric component induced to wafer geometry by the fabrication process; and estimate an asymmetric overlay error induced by the fabrication process based on the asymmetric component detected in wafer geometry.

Process-induced asymmetry detection, quantification, and control using patterned wafer geometry measurements

Predictive modeling based focus error prediction method and system are disclosed. The method includes obtaining wafer geometry measurements of a plurality of training wafers and grouping the plurality of training wafers to provide at least one training group based on relative homogeneity of wafer geometry measurements among the plurality of training wafers. For each particular training group of the at least one training group, a predictive model is develop utilizing non-linear predictive modeling. The predictive model establishes correlations between wafer geometry parameters and focus error measurements obtained for each wafer within that particular training group, and the predictive model can be utilized to provide focus error prediction for an incoming wafer belonging to that particular training group.

Predictive wafer modeling based focus error prediction using correlations of wafers

Systems and methods for predicting and controlling pattern quality data (e.g., critical dimension and/or pattern defectivity) in patterned wafers using patterned wafer geometry (PWG) measurements are disclosed. Correlations between PWG measurements and pattern quality data measurements may be established, and the established correlations may be utilized to provide pattern quality data predictions for a given wafer based on geometry measurements obtained for the give wafer. The predictions produced may be provided to a lithography tool, which may utilize the predictions to correct focus and/or title errors that may occur during the lithography process.

Growing community of inventors

Fremont, CA, United States of America

Pradeep Vukkadala