Applied Materials, Inc.

Kla Tencor Corporation

Pradeep Subrahmanyan

Ady Levy

Sony Varghese

Mark Davis Smith

Myungjun Lee

Srinivas Gandikota

Amnon Manassen

Michael E Adel

Stilian Pandev

Sean S Kang

Mark F Williams

Yixiong Yang

Samir A Nayfeh

Daniel C Wack

Jacqueline S Wrench

Liran Yerushalmi

John Charles Robinson

David Alles

Yong Yang

DongSub Choi

Dzmitry Sanko

Sankuei Lin

William Pierson

Dongsub Choi

Kyuha Shim

Dror Alumot

Luping Huang

Michael J Wright

Hoyoung Heo

Dennis Rodier

Sanjay Kapasi

Stewart A Robertson

Chris Pohlhammer

John Robinson

Michael A Adel

Christopher Pohlhammer

Michael Wright

Provided are methods of reducing the stress of a semiconductor wafer. A wafer map of a free-standing wafer is created using metrology tools. The wafer map is then converted into a power spectral density (PSD) using a spatial frequency scale. The fundamental component of bow is then compensated with a uniform film, e.g., silicon nitride (SiN), deposited on the back side of the wafer.

Stress and overlay management for semiconductor processing

Embodiments herein are directed to localized stress modulation by implanting a first side of a substrate to reduce in-plane distortion along a second side of the substrate. In some embodiments, a method may include providing a substrate, the substrate comprising a first main side opposite a second main side, wherein a plurality of features are disposed on the first main side, performing a metrology scan to the first main side to determine an amount of distortion to the substrate due to the formation of the plurality of features, and depositing a stress compensation film along the second main side of the substrate, wherein a stress and a thickness of the stress compensation film is determined based on the amount of distortion to the substrate. The method may further include directing ions to the stress compensation film in an ion implant procedure.

Localized stress modulation by implant to back of wafer

Embodiments of this disclosure relate to methods for removing a dummy material from under a superlattice structure. In some embodiments, after removing the dummy material, it is replaced with a bottom dielectric isolation layer beneath the superlattice structure.

Methods of forming bottom dielectric isolation layers

A memory device comprises: a stack of alternating silicon oxide layers and wordline layers; each of the wordline layers comprising dipole regions adjacent to the silicon oxide layers, the dipole regions comprising a nitride, a carbide, an oxide, a carbonitride, or combinations thereof of a dipole metal. The dipole regions are formed by driving a dipole film into a gate oxide layer of the wordline layers, and any residual dipole film is removed.

V-NAND stacks with dipole regions

The methods and systems disclosed here detect edges of top-down images of respective cross-sections of an array of high-aspect-ratio (HAR) features. The respective cross sections are at various depths of a HAR feature along a longitudinal direction. The detected edges are re-sampled in a spatial domain at a target angular resolution. The re-sampled edges are represented as a corresponding set of harmonics in a frequency domain, each set of harmonics preserving characteristic information about a respective cross-section of the HAR feature at a certain depth. A plurality of cross-sections at the various depths of the HAR feature are reconstructed by analyzing the corresponding sets of harmonics in the frequency domain. A 3D profile of the HAR feature is generated by stitching the plurality of re-constructed cross-sections at the various depths of the HAR feature.

Construction of three-dimensional profiles of high aspect ratio structures using top down imaging

The methods and systems disclosed here leverage currently available reliable top down imaging techniques used by SEMs and use computational methods to synthesize accurate 3D profiles of features of high aspect ratio structures in a device. Radial cross-sectional profiles obtained from different locations along the lateral direction at different heights/depths are stitched together to create one composite 3D profile of the HAR feature.

A process control system may include a controller configured to receive after-development inspection (ADI) data after a lithography step for the current layer from an ADI tool, receive after etch inspection (AEI) overlay data after an exposure step of the current layer from an AEI tool, train a non-zero offset predictor with ADI data and AEI overlay data to predict a non-zero offset from input ADI data, generate values of the control parameters of the lithography tool using ADI data and non-zero offsets generated by the non-zero offset predictor, and provide the values of the control parameters to the lithography tool for fabricating the current layer on the at least one production sample.

Overlay control with non-zero offset prediction

An apparatus for fixing a wafer, including a chuck having a surface, a plurality of through bores in the chuck extending through the surface of the chuck, a fixed vacuum bellows, and a plurality of floating air bearings, wherein the fixed vacuum bellows and a respective floating air bearing of the plurality of floating air bearings are each individually arranged in separate through bores of the plurality of through bores and elevationally above the surface of the chuck.

Apparatus and method for chucking warped wafers

A lithography system includes an illumination source and a set of projection optics. The illumination source directs a beam of illumination from an off-axis illumination pole to a pattern mask. The pattern mask includes a set of pattern elements to generate a set of diffracted beams including illumination from the illumination pole. At least two diffracted beams of the set of diffracted beams received by the set of projection optics are asymmetrically distributed in a pupil plane of the set of projection optics. The at least two diffracted beams of the set of diffracted beams are asymmetrically incident on the sample to form a set of fabricated elements corresponding to an image of the set of pattern elements. The set of fabricated elements on the sample includes one or more indicators of a location of the sample along an optical axis of the set of projection optics.

Process-sensitive metrology systems and methods

A lithography system includes an illumination source, projection optical elements, and a pattern mask. The illumination source includes one or more illumination poles. The pattern mask includes a set of focus-sensitive mask elements distributed with a pitch and, is configured to diffract illumination from the one or more illumination poles. The pitch may be selected such that two diffraction orders of illumination associated with each of the one or more illumination poles are asymmetrically distributed in a pupil plane of the projection optical elements. Further, the projection optical elements may expose a sample with an image of the set of focus-sensitive pattern mask elements based on the two diffraction orders of illumination associated with each of the one or more illumination poles such that one or more printing characteristics is indicative of a position of the sample within a focal volume of the projection optical elements.

Systems and methods for focus-sensitive metrology targets

A reticle positioning apparatus for actinic EUV reticle inspection including a sealed inspection chamber containing a reticle stage for holding a reticle. The reticle stage has a magnetically suspended upper stage with a long travel in a 'y' direction and a magnetically suspended lower stage with a long travel in an 'x' direction; and a cable stage chamber isolated from the inspection chamber by a cable chamber wall. The cable stage chamber has a cable stage movable in the &#x201c;y&#x201d; direction; and a tube connected at one end to the reticle stage and to the cable stage at the other end. The tube passes from the cable stage through the inspection chamber through a seal in the chamber wall and opening into the cable entry chamber for entry of cables and hoses within the cable stage chamber, which cables and hoses pass through the tube to the reticle stage.

Arrangement of reticle positioning device for actinic inspection of EUV reticles

A method for synchronizing sample stage motion with a time delay integration (TDI) charge-couple device (CCD) in a semiconductor inspection tool, including: measuring a lateral position of a stage holding a sample being inspected; measuring a vertical position of the stage; determining a corrected lateral position of an imaged pixel of the sample based on the measured lateral and vertical positions; and synchronizing charge transfer of the TDI CCD with the corrected lateral position of the imaged pixel.

Apparatus and method for synchronizing sample stage motion with a time delay integration charge-couple device in a semiconductor inspection tool

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Cupertino, CA, United States of America

Pradeep Subrahmanyan