Seagate Technology Incorporated

Lsi Corporation

Maxtor Corporation

Pradeep Padukone

George Mathew

Hongwei Song

Bin Liu

Suharli Tedja

Barrett J Brickner

Various embodiments of the present invention provide systems and methods for phase compensated harmonic sensing. For example, a circuit for harmonics calculation is disclosed that includes a phase difference estimation circuit and a phase offset compensation circuit. The harmonic calculation circuit is operable to calculate a first harmonic based on a periodic data pattern and a second harmonic based on the periodic data pattern. The phase difference estimation circuit operable to calculate a phase difference between the first harmonic and the second harmonic. The phase offset compensation circuit operable to align the second harmonic with the first harmonic to yield an aligned harmonic.

Systems and methods for phase compensated harmonic sensing in fly height control

Methods of calibrating an analog front end (AFE) of a read/write channel include measuring a first magnitude of a test signal, measuring a second magnitude of an output signal of the AFE generated in response to the test signal, and comparing the first magnitude and the second magnitude to generate a measure of a gain of the AFE at a frequency of the test signal. A data storage device includes a read/write head configured to generate an analog input signal, an AFE coupled to the read/write head and configured to amplify and filter the analog input signal, a test signal generator configured to generate a test signal having a frequency substantially equal to a fundamental frequency of the analog input signal or any of its harmonics, and an attenuator coupled between the test signal generator and the AFE.

Calibration of analog front end for gain sensitive measurements

A data storage channel encoder includes a data word input, a code word output and an encoder. The encoder is coupled between the data word input and the code word output and is adapted to encode successive data words received on the data word input into successive code words on the code word output according to a selected code having combined maximum transition run and parity constraints. The maximum transition run constraint constrains the successive code words such that, when the successive code words are concatenated to form an encoded bit stream, the encoded bit stream has a maximum of one consecutive transition beginning at either odd or even indexed bit positions in the encoded bit stream and a maximum of two consecutive transitions beginning at the other of the odd or even indexed bit positions.

Partial response channel having combined MTR and parity constraints

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San Jose, CA, United States of America

Pradeep Padukone