Cadence Design Systems, Inc.

Pradeep Nagaraj

Vivek Chickermane

Brion L Keller

Richard Schoonover

SOC designs increasingly feature IP cores with standardized wrapper cells having vendor-provided test patterns for the internal logic. To test wrapper, interconnect, and other boundary logic, a boundary model is extracted from the design in a synthesis or ATPG environment. Wrapper cells are identified and boundary logic extracted by structural tracing of wrapper chains and tracing from core inputs/outputs to the wrapper cells. A created boundary model excludes core internal logic tested by vendor-provided test patterns to be migrated to the containing chip interface. An SOC ATPG model is built including boundary models for all embedded cores, interconnects, and any other logic residing at the SOC top hierarchical level. This model is very compact yet accurate for testing logic external to all embedded cores. Test time is reduced and test pattern generation greatly simplified, while featuring good test coverage. The same approach is used for 3D packages having multiple dies.

Method and apparatus for automated extraction of a design for test boundary model from embedded IP cores for hierarchical and three-dimensional interconnect test

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Fremont, CA, United States of America

Pradeep Nagaraj