Xilinx, Inc.

Reniac, Inc.

Pradeep Mishra

Somdutt Javre

Siddharth Rele

Gangadhar Budde

Prasanna Sundararajan

Chidamber Kulkarni

Prasanna Sukumar

Rahul Sachdev

Raushan Raj

Vijaya Raghava

Gurshaant Singh Malik

Ajit Mathew

Aditya Alurkar

A database proxy includes a request processor, a cache, a database plugin, and interfaces for coupling the database proxy client devices, other database proxies, and database servers. The request processor is configured to receive a read request from a client, determine whether the read request is assigned to the database proxy, and return results of the read request to the client. When the read request is not assigned to the database proxy, the read request is forwarded to another database proxy. When the read request is assigned to the database proxy, the read request is processed using data stored in the cache when the results are stored in the cache or forwarded to the database plugin, which forwards the read request to a database server, receives the results from the database server, and returns the results to the request processor for storage in the cache.

System and method for a database proxy

Methods and systems are disclosed for determining mask-value pairs for controlling access to a memory segment for a plurality of IDs. A first set of mask-value pairs is determined for a set of allowed identifiers (IDs) and a set of non-allowed IDs. Each mask-value pair of the first set matches at least one ID of the set of allowed IDs and does not match any of the IDs of the set of non-allowed IDs. Redundant mask-value pairs are removed from the first set to produce a second set. Subsets of mask-value pairs in the second set that match the entire set of allowed IDs are determined. The subset having the highest processing efficiency is determined and selected. A set of configuration data is generated that is configured to cause a memory management circuit to enforce access to the memory segment based on the selected subset of mask-value pairs.

Generation of mask-value pairs for managing access to memory segments

Various example implementations are directed to circuits and methods for partitioning a memory for a circuit design in a programmable IC. A user interface is provided for a user to define subsystems, master circuits, memory segments, and permissions for accessing the memory segments by the master circuits. For each defined memory segment, a respective access control entry is generated that includes data for determining master circuits that are permitted access to the memory segment by the user-defined permissions. A first portion of configuration data is generated that is configured to cause a memory management circuit in the programmable IC to enforce access to address ranges, corresponding to the respective memory segments, in a memory of the programmable IC according to the respective access control entries. A second portion of configuration data is generated that is configured to cause programmable resources of the programmable IC to implement the circuit design.

Partitioning memory in programmable integrated circuits

In an approach for determining multiplier values and divisor values for programming frequency multiplier and divider circuits in a clock network, respective requested frequency values and respective tolerance levels relative to the requested frequency values for a plurality of clocked circuit blocks are used. Multiple solution sets are generated, with each solution set including a multiplier value and an associated set of values of divisors, such that resulting actual frequencies satisfy the respective tolerance levels. Respective sets of clocked error values are determined for the plurality of solution sets, with each clocked error value corresponding to a clocked circuit block. Solution-set-error values are determined as a function of the respective sets of clocked error values, and the solution set having the least solution-set-error value is selected and stored.

Determination of configuration values and configuration of frequency multiplier and frequency divider circuitry

Hierarchical preset and rule base configuration of a system-on-chip (SOC) includes receiving a user input selecting a first circuit block of the SOC for enablement and determining, using a processor, a first top level preset according to the user input for the first circuit block. Selected intermediate presets are determined from a plurality of hierarchically ordered presets for the first circuit block. Low level presets are automatically determined for the first circuit block according to the selected intermediate presets for the first circuit block. The low level presets are output, e.g., by loading them into the SOC.

Hierarchical preset and rule based configuration of a system-on-chip

Growing community of inventors

Hyderabad Telangana, India

Pradeep Mishra