Qualcomm Incorporated

Pradeep Kumar Sana

Abhinav Murali

Rakesh Kumar Sinha

Harikrishna Chintarlapalli Reddy

Jibu Varghese K

Sajin Mohamad

A system includes a circuit in a first power domain, a first tri-state inverter having an input coupled to the circuit, and a second tri-state inverter having an input coupled to an output of the first tri-state inverter. The system also includes a level shifter in a second power domain, wherein the level shifter has a first input coupled to the output of the first tri-state inverter and a second input coupled to an output of the second tri-state inverter. The system also includes a shunt switch, a controller, and a pass gate. The shunt switch is coupled between the first input of the level shifter and ground or coupled between the second input of the level shifter and ground. The pass gate is coupled between the controller and the second input of the level shifter or coupled between the controller and the first input of the level shifter.

Freeze enabled swing level shifter

An apparatus, including: an input node; a bias receiver; and a protection device, a gate of the protection device coupled to the bias receiver, the bias receiver tied to a lower voltage domain level, a first source or drain of the protection device coupled to the input node to receive a current from an analog node or a higher voltage domain level from the analog node and a second drain or source of the protection device coupled to a current output node, when the current is received through the input node to the protection device and the lower voltage domain level is in a non-collapse mode, configured to pass the current through the protection device to the current output node.

Voltage aware bias receiver in an analog node

An integrated circuit (IC), including: a current mirror, including: a first field effect transistor (FET) including a first drain, a first gate, and a first source, wherein the first source is coupled to a first voltage rail; and a second FET including a second drain, a second gate, and a second source, wherein the second gate is coupled to the first gate of the first FET, and the second source is coupled to the first voltage rail; and a selective coupling circuit configured to selectively couple the first drain of the first FET to the first and second gates of the first and second FETs based on a voltage at the first drain of the first FET.

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Bengaluru, India

Pradeep Kumar Sana