International Business Machines Corporation

Pradeep Kumar Dubey

Charles Marshall Barton

William John Starke

Terence M Potter

Kathryn Mary O'Brien

John Kevin O'Brien

Thomas R Puzak

Charles Roberts Moore

Jaime Humberto Moreno

Linh Hue Lam

Chiao-Mei Chuang

Mark Jay Charney

A central processing unit (CPU) in a computer that permits speculative parallel execution of more than one instruction thread. The CPU uses Fork-Suspend instructions that are added to the instruction set of the CPU, and are inserted in a program prior to run-time to delineate potential future threads for parallel execution. The CPU has an instruction cache with one or more instruction cache ports, a bank of one or more program counters, a bank of one or more dispatchers, a thread management unit that handles inter-thread communications and discards future threads that violate dependencies, a set of architectural registers common to all threads, and a scheduler that schedules parallel execution of the instructions on one or more functional units in the CPU.

Executing speculative parallel instructions threads with forking and

Dynamic migration of a cache prefetch request is performed. A prefetch candidate table maintains at least one prefetch candidate which may be executed as a prefetch request. The prefetch candidate includes one or more trigger addresses which correspond to locations in the instruction stream where the prefetch candidate is to be executed as a prefetch request. A jump history table maintains a record of target addresses of program branches which have been executed. The trigger addresses in the prefetch candidate are defined by the target addresses of recently executed program branches maintained in the jump history table. A pending prefetch table maintains a record of executed prefetch requests. When an operation such as a cache miss, cache hit, touch instruction or program branch is identified, the pending prefetch table is scanned to determine whether a prefetch request has been executed. If a prefetch request has been executed, the prefetch candidate which was used to execute that prefetch request is updated. That is, a new trigger address in the prefetch candidate is selected in order to reduce access latency.

Automatic cache prefetch timing with dynamic trigger migration

The computer processing unit of the present invention includes a new prefetch instruction, referred to as an STOUCH instruction, which provides the capability to encode compile-time speculations associated with the conditional branches between the time the prefetch request is initiated and the time the prefetched data is actually needed. As a result of this explicit communication of compile-time speculations to the run-time hardware, prefetched lines based on invalid speculations can be discarded earlier, whereas, prefetched lines based on valid speculations can be retained longer in the cache, leading to better cache performance.

Method and apparatus for biasing cache LRU for prefetched

In a computer system having a hierarchical memory, the problem of tolerating cache miss latency is solved by dynamically switching appropriately between two different code sequences, one optimized at compile-time, assuming a cache-hit, and the other optimized at compile-time, assuming a cache-miss. A method for processing instructions and data in a computer system including a hierarchical memory and a static instruction sequence including a memory access instruction and associated memory access latency specific code sequences, each code sequence optimized dependent on an execution of the memory access instruction causing one of a hit or a miss at a level of the memory hierarchy, includes the steps of: decoding and executing the memory access instruction and storing information indicating whether the execution of the memory access instruction caused the hit or the miss; and branching to a cache hit optimized code sequence when the information indicates the hit and a miss optimized code sequence when the information indicates the miss, responsive to the step of storing. Preferably, the memory access latency specific code sequences are associated with one or more identified critical miss-points. The step of branching may be responsive to an inserted branch instruction associated with the memory access instruction. The branch instruction may also specify a level of the cache memory upon which the step of branching is recommended.

Branch on cache hit/miss for compiler-assisted miss delay tolerance

A method and system are provided for processing instruction threads. Execution is initiated by a processing system of a first set of instructions including a particular instruction. The particular instruction includes an indication of a second set of instructions. In response to execution of the particular instruction and to the processing system being of a first type, the processing system continues executing the first set while initiating execution of the second set. In response to execution of the particular instruction and to the processing system being of a second type, the processing system continues executing the first set without initiating execution of the second set.

Growing community of inventors

White Plains, NY, United States of America

Pradeep Kumar Dubey