Rockwell Automation Technologies Incorporated

Sun Microsystems, Inc.

Pradeep Kaushik

Kevin Chao

Richard W Sze

John A Genovesi

Dennis L Wendell

Suresh Seshadri

A scalable industrial data ingestion and analysis architecture integrates and collects data from multiple diverse sources at one or more industrial facilities. Data sources can include plant-level industrial devices and higher-level business systems. The data can be integrated and collected from multiple sources at an on-premise edge or gateway device, which sends the data to event queues on the cloud platform. The data queues orchestrate and store the data on cloud storage, and an analytics layer performs business analytics or other types of analysis on the stored data to produce various outcomes. Similar analytic platforms can also be implemented at the device level, and analytic functions can be scaled between the device level and higher levels in accordance with the scope of a given analytic function.

Scalable industrial analytics platform

Predictive maintenance and process supervision using a scalable industrial analytics platform

Discovery of relationships in a scalable industrial analytics platform

An apparatus and method for controlling and providing a robust, single entry cache memory is described in connection with an on-board cache memory integrated with a microprocessor. By implementing the single entry cache memory in a redundancy array of the cache memory, CPU debug procedures may proceed independently of the cache debug by disabling part of the cache memory and enabling a dedicated single entry cache in the redundancy array. Use of a cache redundancy array for the single entry cache imposes no area or latency penalties because the existing cache redundancy array already matches the latency of the cache.

Method and apparatus for using a fault tolerant memory in processor testing and design

An apparatus and method for controlling and providing off-pitch shifting circuitry for implementing column redundancy in a multiple-array memory is described in connection with an on-board cache memory integrated with a microprocessor. Depending upon the particular sub-array being accessed, shift position data is provided to a shared, off-pitch shift circuit to control the read and/or write operations for the memory. A register bank stores data identifying the defective columns which is compared to the incoming address information to detect any matches. In response to a match, control information is provided to the off-pitch shift circuit for shifting or re-routing the incoming data to a non-defective address in the memory. In this way, defective columns located in different positions in each sub-array can be replaced by redundant paths, thereby repairing the cache and increasing the manufacturing yield of microprocessors with an on-board cache memory.

Off-pitch column redundancy using dynamic shifters

Growing community of inventors

Sunnyvale, CA, United States of America

Pradeep Kaushik