Intel Corporation

Pradeep Dubey

Gary N Hammond

Mustafiz R Choudhury

A memory management system for a computer, where cache coherency between a descriptor cache and data cache is preserved through an inclusion bit mechanism. In one embodiment, an inclusion bit is set for a descriptor cached in a data cache corresponding to a descriptor cached in a descriptor cache such that the association between the descriptors is indicated. Whenever a descriptor in the data cache with a set inclusion bit is altered, the entire descriptor cache is flushed by virtue of the set inclusion bit. Furthermore, in the same embodiment, a valid bit is set for a descriptor in the data cache which is cached from the descriptor table. Whenever a descriptor in the descriptor table, which has a valid bit set in the data cache, is modified, the valid bit is reset. And if the same descriptor with its valid bit reset has a set inclusion bit, then the entire descriptor cache is flushed. As a result, the cache coherency among descriptor cache, data cache and descriptor table is preserved in this improved memory management system.

Growing community of inventors

White Plains, NY, United States of America

Pradeep Dubey