Sandisk Technologies Inc.

Pradeep Anantula

Ankit Rehani

V S N K Chaitanya G

Sridhar Yadala

Sivakumar Grandhi

Venkata Nittala

Vm Shivasubramaniyarajan

Aswani Krishna Addagalla

Aswani Krishna Lakshminarayana Addagalla

VSNKChaitanya G

Systems and methods for converting an input analog signal to a digital representation thereof. A method includes determining an input analog signal voltage range of the input analog signal, and splitting the input analog signal voltage range into n+1 sub-ranges, n being a number of splits in the input analog signal voltage range. The method also includes assigning a respective N-bit coarse digital code i to each sub-range. The method also includes identifying the input analog signal with a corresponding sub-range, the corresponding sub-range having respective digital code i. A delta-sigma operation is performed on the input analog signal using upper and lower reference voltages of the corresponding sub-range that the input analog signal is identified with, to produce the digital representation.

Area-efficient and moderate conversion time analog to digital converter (ADC)

A stage-based frequency optimization for a charge pump achieves a higher area efficiency by operating different stages of the charge pump at their optimized frequency simultaneously, instead of single common frequency, to obtain greater output strength. A first set of stages uses triple well devices as transfer switches and operates at a first, higher frequency. The first stages supply a second set of stages using high voltage devices as transfer switches and operates at a second, lower frequency. The two set of stages are connected through a frequency transition circuit.

Stage based frequency optimization for area reduction of charge pumps

An apparatus and method for detecting leakage current in a non-volatile memory array. A reference current is connected to a leakage detection circuit. A reference code is determined for the leakage detection circuit coupled to a switching circuit. The reference code establishes a leakage current threshold. The reference current is disconnected from the leakage detection circuit and the switching circuit. Next, the leakage detection circuit is connected to a set of word lines of a storage block of a non-volatile memory array by way of the switching circuit. A memory current is generated within the set of word lines. A leakage code is determined for the set of word lines representing leakage current from the word lines in response to the memory current. The leakage code is compared with the reference code. If the leakage code exceeds the reference code, the storage block is deemed unusable.

Non-volatile memory array leakage detection

A charge pump includes first and second multiplier stages including first and second capacitor in series with an input node, a final multiplier stage including an output capacitor in series with the second capacitor and an output node, and pre-charge circuitry. The pre-charge circuitry is configured to charge the output capacitor to a first level during an initial phase of a charging operation, wherein the first level is equal to a supply voltage of the data storage system, and decouple a charging path of the pre-charge circuitry from the output capacitor in response to the output capacitor being charged to the first level. The first and second multiplier stages are configured to increase the charge of the output capacitor to second and third levels higher than the first level during second and third phases of the charging operation.

Growing community of inventors

Bengaluru, India

Pradeep Anantula