Intersil Americas Inc.

Renesas Electronics America Inc.

Prabhjot Singh

Alexander Kalnitsky

Michael D Church

Hosam Haggag

Edgardo A Laber

Long Yu

Xiaodong Zhan

The present embodiments relate generally to DC-DC converters and more particularly to a scheme for providing current sharing between parallel converters in a multiphase configuration. In some embodiments, a cycle-by-cycle instant correction to the compensation signal offset is provided based on the current share error between the paralleled converters so as to achieve improved instant current share performance.

Current sharing scheme in current mode control for multiphase DC-DC converter

A converter includes a buck boost converter circuit to generate an output voltage in response to an input voltage, and an inductor current compensation circuit to generate an output current compensated inductor current signal corresponding to a sensed input current. The output current compensated inductor current signal includes a voltage gap between a boost ramp valley and a buck ramp peak. The buck boost converter circuit includes a current sensor to receive the input voltage, the current sensor to sense an input current corresponding to the input voltage, an upper buck transistor coupled to the input voltage node, an upper boost transistor coupled to an output voltage node to output the output voltage, and an inductor coupled between the upper buck transistor and the upper boost transistor. The inductor current compensation circuit adjusts the voltage gap based on an offset compensation voltage corresponding to a switching frequency.

Ramp offset compensation circuit in a buck boost converter

A buck boost converter includes a buck boost converter circuit to generate an output voltage in response to an input voltage, and a mode control logic circuit to generate a mode control signal to control an operation mode of the buck boost converter circuit to operate in one of a buck mode, a boost mode, and a buck-boost mode. The buck boost converter circuit includes an upper buck transistor coupled to an input voltage node, the input voltage node to receive the input voltage, an upper boost transistor coupled to an output voltage node, the output voltage node to output the output voltage, and an inductor coupled between the upper buck transistor and the upper boost transistor. The mode control signal is generated based on a first duty cycle of the upper buck transistor and a second duty cycle of the upper boost transistor.

Hysteresis timing scheme for mode transition in a buck boost converter

A flash memory array comprises a plurality of memory cells organized in a matrix of rows and columns. Each of the memory cells includes a floating gate memory transistor having a source region and a drain region, and a coupling capacitor electrically connected to the memory transistor. A plurality of word lines are each electrically connected to the capacitor in each of the memory cells in a respective row. A first set of bit lines are each electrically connected to the drain region of the memory transistor in each of the memory cells in a respective column. A plurality of high voltage access transistors are each electrically connected to a bit line in the first set of bit lines. A second set of bit lines are each electrically connected to the source region of the memory transistor in each of the memory cells in a respective column. Various combinations of voltages can be applied to the word lines and the first and second sets of bit lines in operations to erase, program, inhibit, or read the logic state stored by the memory transistor in one or more of the memory cells.

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San Jose, CA, United States of America

Prabhjot Singh