Nxp Usa, Inc.

Freescale Semiconductor,inc.

Nxp B.v.

Prabhjot Singh

Hemant Nautiyal

Mohit Satsangi

Alexandru Marginean

Varun Sethi

Amit Rao

Wasim Khan

Deepak Kumar

David W Todd

Udit Kumar

Tommi Jorma Mikael Jokinen

Poonam Aggrwal

Prabhakar Kushwaha

Robert Freddie Linn-Moran

David Schuchmann

Rajkumar Agrawal

Nutan Kishor Shivhare

Mukesh Bansal

Sudip Jain

Sachin Miglani

Nitin Gera

Prakash Makwana

Facilitating access to a PCIe configuration space of a PCIe function associated with a computer comprises receiving by a PCIe controller EP in the computer over a PCIe link a configuration request from a remote computer to access a PCIe configuration space. The PCIe controller then communicates over a communication fabric the configuration request to a dispatcher of the computer. The dispatcher determines from the configuration request, a PCIe function and operation indicated in the configuration request which is used to identify a respective subsystem to execute the configuration request and the configuration request is communicated to the respective subsystem based on the identification. The subsystem then executes the configuration request to facilitate access to the PCIe configuration space of the PCIe function by the remote computer and sharing of the PCIe function with the remote computer.

System and method to facilitate access by a remote computer to a PCIe configuration space

A bus response to a bus request transmitted by a bus master over a network circuit is received by a bus response modifier. The bus response is transmitted by a bus slave and the bus request and the bus response are associated with a bus transaction over the network circuit. The bus response modifier selects a delay time to delay the bus response to fault test a system and the bus response is delayed by the delay time. A determination is made whether the fault test fails based on the delayed bus response.

Method and system to delay a response associated with a bus transaction that is transmitted to a bus master to perform fault testing

A host data processing system method, apparatus, and architecture are provided for sharing a PCIe EP device with one or more lendee data processing systems in a PCIe cluster by extracting an RID value from a received PCIe transaction message corresponding to a PCIe function at the PCIe endpoint device, and then processing the RID value to identify an interconnect target port value which corresponds to a first lendee data processing system which is sharing the PCIe endpoint device, and then routing the PCIe transaction message through an interconnect on the host data processing system using an interconnect target output port corresponding to the first interconnect target port value to deliver the PCIe transaction message to the first lendee data processing system.

ID-based transaction routing for PCIe endpoint lending

A method to retrieve transaction address resulting in PCIe completion timeout includes monitoring a Peripheral Component Interconnect Express (PCIe) controller to detect a Completion Timeout (CTO) transmitted therefrom. A Master Identification (ID) of a Master and a transaction address of a transaction are stored in a configuration space, in response to detecting the CTO, wherein the transaction originates from the Master and the CTO is signaled in response to the transaction. The CTO is responded to with the Master identified by the Master ID in the configuration space.

Method to retrieve transaction address resulting in an uncorrectable PCIe error

A method, system, apparatus, and architecture are provided for detecting failure of a PCIe endpoint device by scanning an extended configuration space for each connected PCIe endpoint device to detect a first PCIe endpoint device that supports advance status reporting, and then by programming a first predetermined value and a second predetermined value, respectively, into an endpoint response register and a root complex request register of a dedicated memory control word in the extended configuration space for the first PCIe endpoint device, where the second predetermined value signals a request to the first PCIe endpoint device to update the endpoint response register of the dedicated memory control word with a new status value so that, after a minimum specified delay, a report that the first PCIe endpoint device has failed may be generated in response to detecting that the first predetermined value is stored in the endpoint response register.

Method and system to detect failure in PCIe endpoint devices

A system-on-chip includes a processing core and a memory controller connected between the core and an external memory. A clock divider receives an internal clock signal and outputs a divided clock signal. The memory controller uses the divided clock signal to establish an interface communication frequency with the memory. A boot control logic circuit, connected to the clock divider, compares a check data pattern to a predefined data pattern read from the memory by the memory controller at the interface frequency. When the predefined and check data patterns do not match, the boot control logic circuit instructs the clock divider to adjust the divided clock signal to change the interface frequency, after which the predefined data pattern reading and comparison are repeated, and when the predefined and check data patterns match, the memory controller reads a boot program, executed by the core, from the memory at the interface frequency.

System and method for adjusting boot interface frequency

A system provides synchronous read data sampling between a memory and a memory controller, which includes an asynchronous FIFO buffer and which outputs a clock and other control signals. An outbound control signal (e.g., read_enable) is used to time-stamp the beginning of a read access using a clock edge counter. The incoming read data is qualified based on the time-stamped value of the read_enable signal plus typical access latency by counting FIFO pops. The system performs correct data sampling irrespective of propagation delays between the controller and memory. The system may be implemented in a System on a Chip (SOC) device having a synchronous communication system.

Memory controller

A clock generator suitable for use with memory devices enables generation of memory clock signals having odd or even division ratios, an optional phase shift and a 50% duty cycle. First and second clock gate circuits receive a base clock signal and an inverted version thereof, respectively, and are both gated by the output of two comparators that are set when a value of a down counter receiving the base clock signal reaches a predetermined value. The clock gate circuits each include a multiplexer and D-type flip-flop. The output from either flip-flop, or both their outputs 'ORed' together, may be used as a memory clock depending on the desired division ratio and phase shift. The generator is particularly suitable for DDR memory applications that require both edges of the clock signal are evenly placed for launching data on both rising and falling edges.

Clock signal generator

A method and system for booting an electronic device from a NAND flash memory includes a NAND flash controller that receives an event trigger for fetching a pre-boot code stored in the NAND flash memory. Based on the event trigger type, booting parameters are loaded into the controller including a boot frequency of the NAND flash memory. The controller searches for a good memory block in which the pre-boot code is stored by checking the first and second or the first and last pages of a memory block and fetches a portion or the entire pre-boot code based on the event trigger type at the boot frequency.

Method and system for booting electronic device from NAND flash memory

A synchronous data processing system includes a memory module to store data and a memory controller coupled to the memory module. The memory controller includes a clock inverter to receive an input clock signal and to transmit an inverted clock signal to the memory module. The inverted clock signal incurs a first propagation delay prior to reaching the memory module as a memory clock signal. A write data buffer is coupled to the memory module. The write data buffer transmits data to the memory module in response to the input clock signal. An asynchronous first-in-first-out (ASYNC FIFO) buffer is coupled to the memory module. The ASYNC FIFO buffer reads data from the memory module in response to a feedback signal generated by feeding back the memory clock signal to the ASYNC FIFO buffer.

Synchronous data processing system for reliable transfer of data irrespective of propagation delays and process, voltage and temperature (PVT) variations

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Noida, India

Prabhjot Singh