Nxp B.v.

Koninklijke Philips Corporation N.V.

Koninklijke Philips Electronics N.v.

Prabhat Agarwal

Jan Willem Slotboom

Abraham Rudolf Balkenende

Godefridus A M Hurkx

Erwin Hijzen

Radu Surdeanu

Philippe Meunier-Beillard

Godefridus Adrianus Maria Hurkx

Erik Petrus Antonius Maria Bakkers

Gerben Doornbos

Pierre Hermanus Woerlee

Thomas Frach

Jan Sonsky

Anco Heringa

Petrus Hubertus Cornelis Magnee

Rob Van Dalen

Andreas Hubertus Montree

Martijn Henri Richard Lankhorst

Gilberto Curatola

Robertus Theodorus Fransiscus Van Schaijk

Michael A A In'T Zandt

Hans M B Boeve

Nader Akil

Michiel Jos Van Duuren

Robertus T F Van Schaijk

Karen Attenborough

Louis Felix Feiner

Hendrik G A Huizing

Raymond James Duffy

Gerrit Elbert Johannes Koops

Godefridus Hurkx

Raymond Josephus Engelbart Hueting

Erik P A M Bakkers

Godfridus Adrianus Maria Hurkx

Melanie Maria Hubertina Wagemans

Fred Hurkx

Lasse Juhana Kauppinen

The electric device () according to the invention comprises a layer () of a memory material which has an electrical resistivity switchable between a first value and a second value. The memory material may be a phase change material. The electric device () further comprises a set of nanowires (NW) electrically connecting a first terminal () of the electric device and the layer () of memory material thereby enabling conduction of an electric current from the first terminal via the nanowires (NW) and the layer () of memory material to a second terminal () of the electric device. Each nanowire (NW) electrically contacts the layer () of memory material in a respective contact area. All contact areas are substantially identical. The method according to the invention is suited to manufacture the electric device () according to the invention.

Electric device with a layer of conductive material contacted by nanowires

A photosensitive device (), the photosensitive device () comprising a substrate () and a plurality of vertically aligned nanowire diodes (to) provided on and/or in the substrate ().

Photosensitive device and method of manufacturing a photosensitive device using nanowire diodes

A finFET-based non-volatile memory device on a semiconductor substrate includes source and drain regions, a fin body, a charge trapping stack and a gate. The fin body extends between the source and the drain region as a connection. The charge trapping stack covers a portion of the fin body and the gate covers the charge trapping stack at the location of the fin body. The fin body has a corner-free shape for at least &#xbe; of the circumference of the fin body which lacks distinct crystal faces and transition zones in between the crystal faces.

Non-volatile memory device

The invention suggests a transistor () comprising a source () and a drain () as well as a barrier region () located between the source and the drain. The barrier region is separated from the source and the drain by intrinsic or lowly doped regions () of a semiconductor material. Potential barriers are formed at the interfaces of the barrier region and the intrinsic or lowly doped regions. A gate electrode () is provided in the vicinity of the potential barriers such that the effective height and/or width of the potential barriers can be modulated by applying an appropriate voltage to the gate electrode.

Tunneling transistor with barrier

The invention relates to a semiconductor device with a substrate () and a semiconductor body () with a heterojunction bipolar, in particular npn, transistor with an emitter region (), a base region () and a collector region (), which are provided with, respectively, a first, a second and a third connection conductor (), and wherein the bandgap of the base region () is smaller than that of the collector region () or of the emitter region (), for example by the use of a silicon-germanium mixed crystal instead of pure silicon in the base region (). Such a device is characterized by a very high speed, but its transistor shows a relatively low BVeeo. In a device () according to the invention the doping flux of the emitter region () is locally reduced by a further semiconductor region () of the second conductivity type which is embedded in the emitter region (). In this way, on the one hand, a low-impedance emitter contact is ensured, while locally the Gummel number is increased without the drawbacks normally associated with such an increase. In this way, the hole current in the, npn, transistor is increased and thus the gain is decreased. The relatively high gain of a Si&#x2014;Ge transistor is responsible for the low BVCeOf which is consequently avoided in a device () according to the invention. Preferably the further semiconductor region () is recessed in the emitter region (1) and said emitter region () preferably comprises a lower doped part that borders on the base region () and that is situated below the further semiconductor region (). The invention also comprises a method of manufacturing a semiconductor device () according to the invention.

Semiconductor device and method of manufacturing such a device

The invention relates to a semiconductor device with a substrate and a semiconductor body of silicon comprising a bipolar transistor with an emitter region, a base region and a collector region which are respectively of the N-type conductivity, the P-type conductivity and the N-type conductivity by the provision of suitable doping atoms, wherein the base region comprises a mixed crystal of silicon and germanium, the base region is separated from the emitter region by an intermediate region of silicon having a doping concentration which is lower than the doping concentration of the emitter region and with a thickness smaller than the thickness of the emitter region, and the emitter region comprises a sub-region comprising a mixed crystal of silicon and germanium which is positioned at the side of emitter region remote from the intermediate region.

Semiconductor device with a bipolar transistor and method of manufacturing such a device

The invention relates to a semiconductor device () with a semiconductor body () comprising a bipolar transistor with an emitter region, a base region and a collector region () of, respectively, a first conductivity type, a second conductivity type opposite to the first conductivity type, and the first conductivity type. One of the emitter or collector regions () comprises a nanowire (). The base region () has been formed from a layer () at the surface of the semiconductor body (); the other one () of the emitter or collector regions () has been formed in the semiconductor body () below the base region (). The emitter or collector region () comprising the nanowire () has been provided on the surface of the semiconductor body () such that its longitudinal axis extends perpendicularly to the surface.

Semiconductor device and method of manufacturing the same

The invention relates to a semiconductor device () with a substrate () and a semiconductor body () comprising a vertical bipolar transistor with an emitter region, a base region and a collector region () of, respectively, a first conductivity type, a second conductivity type opposite to the first conductivity type and the first conductivity type, wherein the collector region () comprises a first sub-region (A) bordering the base region () and a second sub-region (B) bordering the first sub-region (A) which has a lower doping concentration than the second sub-region (B), and the transistor is provided with a gate electrode () which laterally borders the first sub-region (A) and by means of which the first sub-region (A) may be depleted. According to the invention the collector region () borders the surface of the semiconductor body (), while the emitter region () is recessed in the semiconductor body (), and the collector region () forms part of a mesa structure () formed at the surface of the semiconductor body (). Such a device () has very favorable properties at high frequencies and high voltages and, moreover, is easy to manufacture. In a preferred embodiment the collector () comprises a nanowire () forming the mesa structure ().

A transistor device is formed of a continuous linear nanostructure having a source region, a drain region and a channel region between the source and drain regions. The source () and drain () regions are formed of nanowire ania the channel region () is in the form of a nanotube. An insulated gate () is provided adjacent to the channel region () for controlling conduction i ni the channel region between the source and drain regions.

Nanoscale fet

A tunnel transistor includes source diffusion () of opposite conductivity type to a drain diffusion () so that a depletion layer is formed between source and drain diffusions in a lower doped region (). An insulated gate () controls the position and thickness of the depletion layer. The device includes a quantum well formed in accumulation layer () which is made of a different material to the lower layer () and cap layer ().

Tunnel field effect transistor

A transistor comprises a nanowire () having a source () and a drain () separated by an intrinsic or lowly doped region (). A potential barrier is formed at the interface of the intrinsic or lowly doped region () and one of the source () and the drain (). A gate electrode () is provided in the vicinity of the potential barrier such that the height of the potential barrier can be modulated by applying an appropriate voltage to the gate electrode ().

Nanowire tunneling transistor

A radiation detector () includes a semiconductor layer(s) () formed on a substrate () and a scintillator () formed on the semiconductor layer(s) (). The semiconductor layer(s) () includes an n-doped region () disposed adjacent to the substrate (), and a p-doped region () disposed adjacent to the n-doped region (). A trench () is formed within the semiconductor layer(s) () and around the p-doped region () and is filled with a material () that reduces pn junction curvature at the edges of the pn junction, which reduces breakdown at the edges. The scintillator () is disposed over and optically coupled to the p-doped regions (). The radiation detector () further includes at least one conductive electrode () that electrically contacts the n-doped region.

Implementation of avalanche photo diodes in (Bi)CMOS processes

A avalanche mode photodiode array () is fabricated using a silicon on insulator wafer and substrate transfer process. The array includes a plurality of photodiodes (). The photodiodes () include an electrically insulative layer (), a depletion region (), and first () and second () doped regions. An interconnection layer () includes electrodes () which provides electrical connections to the photodiodes. The photodiode array () is carried by a handle wafer ().

Geiger mode avalanche photodiode

A metal-base transistor is suggested. The transistor comprises a first and a second electrode () and base electrode () to control current flow between the first and second electrode. The first electrode () is made from a semiconduction material. The base electrode () is a metal layer deposited on top of the semiconducting material forming the first electrode. According the invention the second electrode is formed by a semiconducting nanowire () being in electrical contact with the base electrode ().

Metal-base nanowire transistor

The invention relates to a semiconductor device () with a semiconductor body () comprising a bipolar transistor with an emitter region (), a base region () and a collector region () of, respectively, a first conductivity type, a second conductivity type, opposite to the first conductivity type, and the first conductivity type, wherein, viewed in projection, the emitter region () is positioned above or below the base region (), and the collector region () laterally borders the base region (). According to the invention, the base region () comprises a highly doped subregion (A) the doping concentration of which has a delta-shaped profile in the thickness direction, and said highly doped sub-region (A) extends laterally as far as the collector region (). Such a lateral bipolar transistor has excellent high-frequency properties and a relatively high breakdown voltage between the base and collector regions (), implying that the device is suitable for high power applications. The doping concentration lies preferably between about 10and about 10at/cm, and the thickness of the sub-region (A) lies between 1 and 15 nm and preferably between 1 and 10 nm. The invention also comprises a method of manufacturing such a device ().

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Prabhat Agarwal