Nokia Corporation

Nokia Intelligent Edge Routers Inc.

Prabhas Kejriwal

Chi Fai Ho

Shashank C Merchant

Ravi Bail Bhat

Amar S Gupta

Lalit Merani

Raghu R Kondapalli

Ravi Ramesh Bhat

Gautam Dewan

Manish Muthal

Guatam Dewan

A jitter buffer receives a plurality of data packets comprising a circuit emulation service over internet protocol (CESIP), buffers the plurality of data packets, and plays data from the plurality of data packets at a constant bit rate corresponding to the CESIP.

Jitter buffer for a circuit emulation service over an internal protocol network

A micro-programmable controller is disclosed for parsing a packet and encapsulating data to form a packet. The micro-programmable controller loads an instruction within the micro-controller. The instruction word has a plurality of instruction fields. The micro-controller processes the plurality of instruction fields in parallel. Each instruction field is related to a specific operation for parsing a packet or encapsulating data to form a packet. The programmable micro-controller can be programmed to handle packets to support new types of protocols by programming a template to string specific routines together based on an instruction set specific for parsing and encapsulating.

Micro-programmable protocol packet parser and encapsulator

Jitter buffer for a circuit emulation service over an internet protocol network

An apparatus is described having an output packet organizer that has a first location and a plurality of second locations. The first and second locations correspond to the priority of a packet, where the first location has higher priority than the second locations. The output packet organizer has a third location. The third location has a higher priority than the first location. The first and third locations are coupled to a scheduler that serves the first and third locations. The second locations coupled to the scheduler through a round robin pointer.

Method and apparatus for an output packet organizer

One embodiment of the present invention receives a plurality of network services, maps the plurality of network services to a single network service at a network layer higher than layer, and transmits the single network service. Another embodiment of the present invention receives a single network service at a network layer higher than layer, maps the single network service to a plurality of network services, and transmits the plurality of network services.

Multiple services emulation over a single network service

A method is described that involves presenting packet header information from a packet and packet size information for the packet to a pipeline that comprises multiple stages. One of the stages identifies, with the packet header information, where input flow information for the packet is located. The input flow information is then fetched. The input flow information identifies where input capacity information for the packet is located and the input capacity information is then fetched. Another of the stages compares an input capacity for the packet with the packet's size and indicates whether the packet is conforming or non-conforming based upon the comparison. The input capacity is calculated from the input capacity information.

Method and apparatus for input rate regulation associated with a packet processing pipeline

The present invention establishes a circuit emulation service (CES) over an internet protocol (IP) network based on properties of the IP network. The CES emulates a circuit from a local interworking function to a remote interworking function. Data that is received at a constant bit rate at the local interworking function is encapsulated into a number of IP packets configured according to the CES. The IP packets are transported from the local interworking function to the remote interworking function according to the CES. In one embodiment, each IP packet also includes data segments for simultaneously encapsulating multiple constant bit rate circuits. In another embodiment, each data segment includes a separate CES circuit header.

Circuit emulation service over an internet protocol network

Method and apparatus for output rate regulation and control associated with a packet pipeline

A cell processing pipeline is described having a plurality of stages for cell reassembly. The cell has a cell header and a cell payload. One of the stages is configured to parse packet header information located within the cell payload.

Growing community of inventors

Palo Alto, CA, United States of America

Prabhas Kejriwal