Lsi Logic Corporation

Prabhakar Pati Tripathi

Bruce Joseph Whitefield

Chi-Hung Wang

Zhihai Wang

Ruggero Castagnetti

Ramnath Venkatraman

Weidan Li

Ashok K Kapoor

Gobi R Padmanabhan

Nicholas K Eib

Keith K Chao

Thomas G Mallon

Ratan K Choudhury

Gauri C Das

A method of forming a metallization interconnection system within a via. A first liner layer of titanium is deposited to a first thickness in the following manner. A substrate containing the via is placed within an ion metal plasma deposition chamber that contains a titanium target. The ion metal plasma deposition chamber is evacuated to a first base pressure. A first flow of argon is introduced to the ion metal plasma deposition chamber at a first deposition pressure. The substrate is biased to a first voltage. A plasma within the ion metal plasma deposition chamber is energized at a first power for a first length of time. A second liner layer of TiNis deposited to a second thickness on top of the first liner layer of titanium in the following manner. A first flow of nitrogen and a second flow of argon are introduced to the ion metal plasma deposition chamber at a second deposition pressure. The substrate is biased to a second voltage. The plasma within the ion metal plasma deposition chamber is energized at a second power for a second length of time, after which the substrate is removed from the ion metal plasma deposition chamber. Finally, a third liner layer of titanium nitride is deposited in a second deposition chamber, and a plug of tungsten is deposited.

Low via resistance system

The present invention provides a method of forming a semiconductor device fuse and a semiconductor device fuse structure. A first dielectric layer is formed on top of a metal layer in a semiconductor device. The dielectric layer is patterned to provide access to at least two contacts in the metal layer. A conductive metal layer is deposited and patterned to form a fuse between the fuse contacts. A second dielectric layer is deposited on the conductive metal layer.

Method of forming metal fuses in CMOS processes with copper interconnect

A method of forming a metallization interconnection system within a via. A first liner layer of titanium is deposited to a first thickness in the following manner. A substrate containing the via is placed within an ion metal plasma deposition chamber that contains a titanium target. The ion metal plasma deposition chamber is evacuated to a first base pressure. A first flow of argon is introduced to the ion metal plasma deposition chamber at a first deposition pressure. The substrate is biased to a first voltage. A plasma within the ion metal plasma deposition chamber is energized at a first power for a first length of time. A second liner layer of Ti N is deposited to a second thickness on top of the first liner layer of titanium in the following manner. A first flow of nitrogen and a second flow of argon are introduced to the ion metal plasma deposition chamber at a second deposition pressure. The substrate is biased to a second voltage. The plasma within the ion metal plasma deposition chamber is energized at a second power for a second length of time, after which the substrate is removed from the ion metal plasma deposition chamber. Finally, a third liner layer of titanium nitride is deposited in a second deposition chamber, and a plug of tungsten is deposited.

Disclosed is the formation of additional lines, either dummy lines or active lines, in an electrically conductive pattern of lines to provide more uniform loading for either etching or chemical/mechanical polishing of a layer of electrically conductive material from which the pattern of lines is formed. Also disclosed is the use of additional or dummy vias to balance the loading during etching of the vias, as well as to provide stress relief for underlying metal in regions or areas having a low density of vias. Further disclosed is the use of a working grid on the integrated circuit structure to analyze the spacing of lines or vias for the above effects.

Method for adjusting the density of lines and contact openings across a

A method of forming a metallization system in which ohmic contact is made to a silicon surface is described. A first layer of titanium is formed over the silicon surface. This first titanium layer is subsequently annealed in a nitrogen atmosphere to convert a first portion of the layer to a layer of titanium silicide, and a second portion to a first layer of titanium nitride. The titanium silicide layer provides for the formation of an ohmic contact between the metallization system and the silicon surface. The first titanium nitride layer provides for a degree of spike resistance between the silicon surface and the metallization system. A second layer of titanium nitride is formed over the first titanium nitride layer. This second titanium nitride layer provides further spike resistance between the silicon surface and the metallization system. A second titanium layer is then formed over the second titanium nitride layer, and acts to wet the surface of the second layer of titanium nitride, and aides in the flow of subsequently deposited layers across the second titanium nitride layer. An aluminum layer is formed over the second titanium layer, for providing a low ohmic resistance path for the flow of electrons through the metallization system. Finally, a third titanium nitride layer is formed over the aluminum layer.

Method of forming a high electromigration resistant metallization system

A method of interactive feedback in semiconductor processing is provided which compensates for lithographic proximity effects, reactive ion etch loading effects, electromigration and stress due to layering.

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Santa Clara, CA, United States of America

Prabhakar Pati Tripathi