International Business Machines Corporation

Synopsys, Inc.

Prabhakar Nandavar Kudva

Pradip Bose

Hans Mikael Jacobson

Stanley Everett Schuster

Peter William Cook

Alper Buyuktosunoglu

Chen-Yong Cher

Deborah A Neumayer

Nicholas C M Fuller

David Shing-Ki Kung

Pia Naoko Sanda

Philip George Emma

Mark Alan Lavin

Meikei Ieong

Jude A Rivers

Victor V Zyuban

Kathryn Wilder Guarini

Ibrahim M Elfadel

Wilm Ernst Donath

Leon Stok

Andrew James Sullivan

Syed M Alam

Arifur Rahman

Lukas P P P Van Ginneken

Chung H Lam

Vittorio R Castelli

David James Hathaway

Naresh Nayar

Matthew Joseph Breitwisch

Wei Hwang

Vijayalakshmi Srinivasan

Robert Brett Tremaine

Ruchir Puri

K Paul Muller

Paul Gerard Villarrubia

Rajesh Ramkrishna Bordawekar

Lakshmi Narasimha Reddy

Jian J Xu

Mark Anthony Check

Brian William Curran

James Xenidis

Lawrence David Bergman

Joseph W Ligman

John-David Wellman

Venkat K Balagurusamy

Leon Jacob Sigal

Daniel Arthur Prener

Tessa Ann Lau

John Andrew Schumann

Daniel A Oblinger

Nathaniel Douglas Hieter

Eli Arbel

Vince Siu

Donna N Eng Dillenberger

Sean Michael Carey

Zhigang Hu

Shiri Moran

James Lee Van Oosten

Daniel James Henderson

Victor N Kravets

David W Siegel

Jeffrey W Kellington

Matthew Harrison Tong

Mark D Mayo

Naoko Pia Sanda

Reinaldo A Bergamaschi

Kanad Chakraborty

Ashwin Dhinesh Kumar

Meeta S Gupta

Sahil Dureja

William E Dougherty

Matthew E Mariani

Daniel M Citron

Systems, computer-implemented methods or computer program products to facilitate receiving results of a semantic structured query language (SQL) query and employing sparse hash-table based sketches to interpret a semantic structured query language (SQL) query result. A computing component stores a first space-efficient structure sketch in a compressed serialize form. The computing component can load a second space-efficient data structure sketch along with the first space-efficient data structure sketch and can compute one or more interpretability scores by extracting co-occurrence information from the first space-efficient data structure sketch. The second space-efficient data structure sketch can include a sketch for containment check.

Scalable count based interpretability for database artificial intelligence (AI)

A method, a computer program product, and a computer system for classifying bacteria. The method comprises extracting a morphology signature corresponding to one or more bacteria and extracting a motility signature corresponding to the one or more bacteria. The method further comprises merging the morphology signature and the motility signature into a merged vector signature and classifying the one or more bacteria based on the merged vector signature.

Bacteria classification

Techniques facilitating blockchain ledgers of material spectral signatures for supply chain integrity management are provided. In one example, a computer-implemented method comprises validating, by a device operatively coupled to a processor, spectral signature data associated with a material, resulting in validated spectral signature data; and generating, by the device, a set of information corresponding to a transaction of the material in a blockchain associated with the material, wherein the set of information is related to the validated spectral signature data. In some embodiments, the computer-implemented method further comprises authenticating, by the device, a first party device associated with a first party to the transaction and a second party device associated with a second party to the transaction and including identities of the first party and the second party as indicated by the respective party devices in the set of information.

Blockchain ledgers of material spectral signatures for supply chain integrity management

An automated method for designing an integrated circuit layout using a computer based upon an electronic circuit description and based upon cells which are selected from a cell library, each of the cells having an associated area, comprising the steps of: (a) placing each of the cells in the integrated circuit layout so that the cells can be coupled together by wires to form a circuit path having an associated predetermined delay constraint wherein the cells are coupled together based upon the electronic circuit description input to the computer; (b) connecting the cells together with the wires to form the circuit path; and (c) adjusting an area of at least one of the cells to satisfy the associated predetermined delay constraint of the circuit path.

Timing closure methodology including placement with initial delay values

A mechanism is provided for validating overall resilience and security characteristics of a sub-component chip design. For each instance of a resiliency template identified as appearing in a design netlist of the sub-component chip design thereby forming one or more identified resiliency sections, a determination is made as to whether an output of the design netlist where an error signal is output interconnects to the one or more identified resiliency sections of the design netlist. Responsive to the one or more identified resiliency sections interconnecting to the output of the design netlist where the error signal is output, one or more identified resiliency sections are marked as being protected by the error signal. An identification of the one or more identified resiliency sections and an identification of the error signal protecting the one or more identified resiliency sections are output to a design team.

Template matching for resilience and security characteristics of sub-component chip designs

Mechanisms are provided for predicting effects of soft errors on an integrated circuit device design. A data processing system is configured to implement a unified derating tool that includes a machine derating front-end engine used to generate machine derating information, and an application derating front-end engine used to generate application derating information, for the integrated circuit device design. The machine derating front-end engine executes a simulation of the integrated circuit device design to generate the machine derating information. The application derating front-end engine executes an application workload on existing hardware similar in architecture to the integrated circuit device design and injects a fault into the existing hardware during execution of the application workload to generate application derating information. The machine derating information is combined with the application derating information to generate at least one soft error rate value for the integrated circuit device design.

Hardware execution driven application level derating calculation for soft error rate analysis

An attribute of a descriptor associated with a task informs a runtime environment of which instructions a processor is to run to schedule a plurality if resources for completion of the task in accordance with a level of quality of service in a service level agreement.

Tunable error resilience computing

A system and method for controlling power and performance in a microprocessor system includes a monitoring and control system integrated into a microprocessor system. The monitoring and control system includes a hierarchical architecture having a plurality of layers. Each layer in the hierarchal architecture is responsive to commands from a higher level, and the commands provide instructions on operations and power distribution, such that the higher levels provide modes of operation and budgets to lower levels and the lower levels provide feedback to the higher levels to control and manage power usage in the microprocessor system both globally and locally.

Method and system for controlling power in a chip through a power performance monitor and control unit

An efficient method for selecting a minimal and statistically relevant set of SER sensitive logic devices critical to the SER robustness for a design, through identification by device type, identification nomenclature, connectivity and context. The minimal set of devices comprise the set of fault injection test points using a conventional fault injection test verification environment to establish an SER induced failure rate a logic design. The selection method affords a design independent means to evaluate any design regardless of the origin, source language or documentation by working at the common logic device level 'gate-level' netlist format for the design data. The selected set of devices is distilled from the design data by successively filtering the design through a series of heuristic rule-based device identifier computer programs that group and annotate the devices into specific database records. These records are then used to organize the fault injection device test set by test behavior and relevance.

Verification of soft error resilience

Method and system for controlling power in a chip through a power-performance monitor and control unit

Mechanisms for modeling system level effects of soft errors are provided. Mechanisms are provided for integrating device-level and component-level soft error rate (SER) analysis mechanisms with micro-architecture level performance analysis tools during a concept phase of the IC design to thereby generate a SER analysis tool. A first SER profile for the IC design is generated by applying the SER analysis tool to the IC design. At a later phase of the IC design, detailed information about SER vulnerabilities of logic and storage elements within the IC design are obtained and the first SER profile is refined based on the detailed information about SER vulnerabilities to thereby generate a second SER profile for the IC design. Modifications to the IC design are made at one or more phases of the IC design based on one of the first SER profile or the second SER profile.

Modeling system-level effects of soft errors

A test system tests a full system integrated circuit (IC) model that includes a device under test (DUT) IC model and a support IC model. A test manager information handling system (IHS) maps the full system IC model on a hardware accelerator simulator via an interface bus. The hardware accelerator simulator thus emulates the full system IC model. Of all possible fault injection points in the model, the test manager IHS selects a subset of those injection points for fault injection via a statistical sampling method in one embodiment. In response to commands from the test manager IHS, the simulator serially injects faults into the selected fault injection points. The test manager IHS stores results for respective fault injections at the selected injection points. If a machine checkstop or silent data corruption error occurs as a result of an injected fault, the DUT IC model may return to a stored checkpoint and resume operation from the stored checkpoint. The result information is useful in determining a soft error rate (SER) for the DUT IC.

Method and apparatus for testing a full system integrated circuit design by statistical fault injection using hardware-based simulation

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Warwick, NY, United States of America

Prabhakar Nandavar Kudva