Dell Products Inc.

PoYu Cheng

Wei G Liu

David Keith Chalfant

Yu-Hsuan Yang

Yaohui Hung

Yu-Cheng Sheng

An information handling system includes a BIOS and a service processor. The BIOS may generate, during a POST, a secret key that includes a symmetric key and a HMAC key and transmits the secret key to the service processor via an high-speed communication interface. After the POST, the BIOS transmits an SMI message that includes an encrypted message and a first hash value of the encrypted message. The encrypted message is encrypted using the symmetric key and the first hash value of the encrypted message is calculated using the HMAC key. The service processor calculate a second hash value of encrypted message based on the HMAC key and verify the encrypted message by comparing the first hash value and the second hash value. After a successful verification, the service processor decrypts the encrypted message and transmits a response to the BIOS.

Secure high-speed communication interface between a basic input and output system and a service processor

Controlling access to an ERST, including: triggering, in response to an occurrence of an error, a SMI; adjusting, in response to the SMI and by a SMM RAS handler module, a slate of an access gate from a locked state to an unlocked state, the access gate controlling access to an ERST storage region; generating, by an OS MCE handler, an error record based on the error; accessing, by the OS MCE handler, an ACPI ERST to identify instructions for storing the error record at the ERST storage region; triggering, in response to the instructions and by the OS MCE handler, an additional SMI; determining, in response to the additional SMI and by a SMM handler, that the access gate is in the unlocked state; in response to determining that the access gate is in the unlocked state: storing, by the SMM handler, the error record at the ERST.

Controlling access to an error record serialization table of an information handlng system

In general, embodiments disclosed herein relate to using high bandwidth memory (HBM) in a booting process. In embodiments disclosed herein, a region of the HBM is set aside as an additional memory pool (also referred to as a pool) for drivers and/or other memory heap requests in the booting process. One or more embodiments maintain the existing memory pool below four GB, but provide an additional resource for drivers and heap requests.

System and method to utilize high bandwidth memory (HBM)

A method may include, in an information handling system comprising a basic input/output system (BIOS) embodied in non-transitory computer-readable media and configured to be the first code executed by a processor when the information handling system is booted and configured to initialize components of the information handling system into a known state: receiving an indication of installation of a protocol by a producer driver of a plurality of protocol drivers integral to the BIOS, storing metadata regarding the protocol in a protocol database of the BIOS, receiving a request to consume the protocol by a consumer driver of the plurality of protocol drivers, and obfuscating the metadata stored in the protocol database from the consumer driver to prevent the consumer driver from uninstalling the protocol.

Growing community of inventors

Tainan, Taiwan

PoYu Cheng