Texas Instruments Corporation

Geophysical Service Inc.

Powell L Calder

An input/output command processor provides a sophisticated communication link between a central processor and peripheral digital apparatus. The command processor receives commands from the central processor, interprets them and transmits them to the peripheral digital apparatus. The command processor is comprised of a store/fetch circuit for directly accessing the memory of the central processor; a fetch and buffer circuit for causing a fetch and for temporarily storing the results of the fetch (commands) in a buffer register file; an interpret controller for interpreting the commands and routing them to the cognizant peripheral apparatus, according to their function.

Input/output command processor

A device interface controller provides a sophisticated communication link between a central processor and peripheral digital apparatus. The device interface controller provides simultaneous read and write operations with the peripheral digital apparatus. The device interface controller communicates with the peripheral digital apparatus, providing data to that apparatus and receiving data from that apparatus, as well as commanding the apparatus to perform functions peculiar to the selected device.

Device interface controller for input/output controller

An input process sequence controller provides a sophisticated communication processing link between a central processor and peripheral digital apparatus. Data is transmitted from the peripheral digital apparatus to the process sequence controller whose function is to process that incoming data as commanded, to relieve the central processor of that task. The process sequence controller has a processor unit, controlled by a Read-only Memory for performing certain functions on the incoming data. The incoming data is received by one portion of a first swapping buffer while a second portion transmits previously received data to the processor unit. When the second portion is emptied, it begins receiving data while the first portion transmits data. A first portion of a second swapping buffer receives processed data from the processor unit while a second portion transmits processed data to the central processor. When the second portion is emptied, it begins receiving processed data while the first portion transmits its processed data. This procedure continues during an operation.

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Powell L Calder