International Business Machines Corporation

Globalfoundries Inc.

Elpis Technologies Inc.

Samsung Electronics Co., Ltd.

Adeia Semiconductor Bonding Technologies Inc.

Pouya Hashemi

Alexander Reznicek

Kangguo Cheng

Karthik Balakrishnan

Ali Khakifirooz

Takashi Ando

Choonghyun Lee

Bruce Bennett Doris

Jingyun Zhang

Tak H Ning

Bahman Hekmatshoartabari

Shogo Mochizuki

Keith E Fogel

Stephen W Bedell

Ruilong Xie

Dominic Joseph Schepis

John Albrecht Ott

Nathan P Marchack

Kevin K Chan

Jeng-Bang Yau

Chandrasekharan Kothandaraman

Veeraraghavan S Basker

Vijay Narayanan

Michael A Guillorn

Lukas Czornomaz

Mahmoud M Khojasteh

Sanghoon Lee

Effendi Leobandung

Ali Afzali-Ardakani

Hemanth Jagannathan

Thomas N Adam

Anirban Basu

Jonathan Zanhong Sun

Kam-Leung Lee

Martin Michael Frank

Min Yang

Dae-Gyu Park

Charan V V S Surisetty

Veeresh Vidyadhar Deshpande

Adra Carr

Vladimir Djara

Tenko Yamashita

Nicolas J Loubet

Ruqiang Bao

Hong He

Daniel Christopher Worledge

Cheng-Wei Cheng

Renee Tong Mo

Pranita Kerber

Joshua M Rubin

Miaomiao Wang

Matthias Georg Gottwald

Lisa F Edge

John Bruley

Eric Raymond Evarts

Virat Vasav Mehta

SangHoon Shin

Robin M Schulz

Jeffrey W Sleight

Guy M Cohen

Eugene John O'Sullivan

John Kenneth DeBrosse

Talia S Gershon

Guohan Hu

Michael F Lofaro

Yanning Sun

Raghavasimhan Sreenivasan

Darsen D Lu

Janusz Jozef Nowak

Dimitri Houssameddine

Eileen Ann Galligan

Saba Zare

Christine Qiqing Ouyang

Kotb Jabeur

Christopher Safranski

Thitima Suwannasiri

A field effect device is provided. The field effect device includes a semiconductor nanosheet segment above a substrate, and a T-shaped inner spacer on the semiconductor nanosheet segment. The field effect device further includes a gate dielectric layer on the semiconductor nanosheet segment, and a first work function material plug on the gate dielectric layer. The field effect device further includes a second work function material layer on the first work function material plug and a center portion of the gate dielectric layer, wherein the second work function material layer is a different work function material from the first work function material plug.

Nanosheet device with T-shaped dual inner spacer

Embodiments are disclosed for a three-terminal spin-orbit-torque (SOT) magnetoresistive random access memory (MRAM) device. The three-terminal SOT MRAM device includes a first type field effect transistor (FET) that drives an SOT line. Additionally, the first type FET includes a write gate in electrical contact with a write wordline (WWL). Further, the device also includes a second type FET in electrical contact with a magnetic tunnel junction (MTJ). Also, the second type FET comprises a read gate in electrical contact with a read wordline (RWL). Additionally, the first type FET is disposed above the second type FET. Further, the three-terminal SOT MRAM device provides a density of three contacted poly pitch (CPP) per two cells.

Stacked FET with three-terminal SOT MRAM

A magnetic random access memory (MRAM) apparatus and method are provided. The apparatus includes a magnetic tunnel junction (MTJ) stack; a spin-orbit-torque (SOT) layer that underlies the MTJ stack; and a dielectric pillar that underlies the SOT layer and the MTJ stack. The SOT layer has a stepped profile. The method includes forming a dielectric base of a first dielectric material and a dielectric pillar of a second dielectric material, wherein the dielectric pillar protrudes from the dielectric base, forming a first intermediate structure by depositing a first layer of conductive material onto the dielectric base, sufficiently thick to cover the pillar and the base, forming a planarized structure by planarizing the first intermediate structure to reveal the pillar, and depositing a second layer of spin-orbit-torque metal onto the planarized structure.

Spin-orbit-torque (SOT) MRAM with doubled layer of SOT metal

Embodiments of the invention are directed to a structure that includes a resistive switching device (RSD). The RSD includes a first terminal having an outer sidewall surface; a second terminal; an active region having a switchable conduction state; and a first protective layer on the outer sidewall surface of the first terminal.

Resistive switching device having a protective electrode ring

Embodiments of the invention are directed to a transistor device that includes a channel stack having stacked, spaced-apart, channel layers. A first source or drain (S/D) region is communicatively coupled to the channel stack. A tunnel extends through the channel stack, wherein the tunnel includes a central region and a first set of end regions. The first set of end regions is positioned closer to the first S/D region than the central region is to the first S/D region. A first type of work-function metal (WFM) is formed in the first set of end regions, the first WFM having a first work-function (WF). A second type of WFM is formed in the central region, the second type of WFM having a second WF, wherein the first WF is different than the second WF.

Using different work-functions to reduce gate-induced drain leakage current in stacked nanosheet transistors

Channel engineering is employed to obtain a gate-all-around field-effect transistor having an asymmetric threshold voltage. A dual channel profile enables a steep potential distribution near the source side that enhances the lateral channel electric field and thus increases the carrier mobility.

Gate-all-around field-effect transistor having source side lateral end portion smaller than a thickness of channel portion and drain side lateral end portion

An approach to provide a structure of a double magnetic tunnel junction device with two spacers that includes a bottom magnetic tunnel junction stack, a spin conducting layer on the bottom magnetic tunnel junction stack, a top magnetic tunnel junction stack on the spin conduction layer, a first dielectric spacer on sides of the top magnetic tunnel junction stack and a portion of a top surface of the spin conduction layer, and a second dielectric spacer on the first spacer. The double magnetic tunnel device includes the top magnetic tunnel junction stack with a width that is less than the width of the bottom magnetic tunnel junction stack.

Dual spacer for double magnetic tunnel junction devices

A spin-orbit torque magnetoresistive random-access memory device formed by forming an array of transistors, where a column of the array includes a source line contacting the source contact of each transistor of the column, forming a spin-orbit-torque (SOT) line contacting the drain contacts of the transistors of the row, and forming an array of unit cells, each unit cell including a spin-orbit-torque (SOT) magnetoresistive random access memory (MRAM) cell stack disposed above and in electrical contact with the SOT line, where the SOT-MRAM cell stack includes a free layer, a tunnel junction layer, and a reference layer, a diode structure above and in electrical contact with the SOT-MRAM cell stack, an upper electrode disposed above and in electrical contact with the diode structure.

Spin-orbit-torque magnetoresistive random-access memory array

A semiconductor device including a second magnetic tunnel junction stack aligned above a spin conductor layer above a first magnetic junction stack, a sidewall dielectric surrounding the second magnetic tunnel junction stack, a vertical side surface of the sidewall dielectric is aligned with vertical side surfaces of the spin conductor layer and the first magnetic junction stack. A method including forming a first magnetic tunnel junction stack, a spin conductor layer and a second magnetic tunnel junction stack, patterning the second magnetic tunnel junction stack, while not patterning the spin conductor layer and the first magnetic tunnel junction stack, forming a sidewall dielectric and a polymer layer on the sidewall dielectric. A method including patterning a second magnetic tunnel junction stack, while not patterning a spin conductor layer below the second magnetic tunnel junction stack nor a first magnetic tunnel junction stack below the spin conductor layer.

Wide-base magnetic tunnel junction device with sidewall polymer spacer

A method of forming two or more nano-sheet devices with varying electrical gate lengths, including, forming at least two cut-stacks including a plurality of sacrificial release layers and at least one alternating nano-sheet channel layer on a substrate, removing a portion of the plurality of sacrificial release layers to form indentations having an indentation depth in the plurality of sacrificial release layers, and removing a portion of the at least one alternating nano-sheet channel layer to form a recess having a recess depth in the at least one alternating nano-sheet channel layers, where the recess depth is greater than the indentation depth.

Fabrication of nano-sheet transistors with different threshold voltages

A memory structure, i.e., magnetoresistive random access memory (MRAM) structure, is provided that includes a seeding area including at least a tunnel barrier seed layer located beneath a chemical templating layer that is wider than the magnetic tunnel junction (MTJ) structure that is located on the chemical templating layer. Redeposited metallic material is located on at least a sidewall of the tunnel barrier seed layer of the seeding area so as to shunt that area of the structure. The memory structure has reduced resistance with minimal tunnel magnetoresistance (TMR) loss penalty.

MRAM structure with enhanced magnetics using seed engineering

A semiconductor device including a magnetic tunnel junction stack, a metallic hard mask aligned above the magnetic tunnel junction stack and an air gap surrounding the metallic hard mask. A method including forming a magnetic tunnel junction stack, forming a metallic hard mask aligned above the magnetic tunnel junction stack, conformally forming a dielectric over the metallic hard mask and the magnetic tunnel junction stack, forming barrier on vertical side surfaces of the dielectric, and removing the dielectric between the metallic hard mask and the barrier. A method including forming a magnetic tunnel junction stack, forming a metallic hard mask aligned above the magnetic tunnel junction stack, conformally forming a dielectric over the metallic hard mask and the magnetic tunnel junction stack, selectively removing a portion of the dielectric surrounding the metallic hard mark.

Magnetic tunnel junction device with air gap

A spin-orbit torque magnetoresistive random-access memory device formed by fabricating a spin-Hall-effect (SHE) layer above and in electrical contact with a transistor, forming a spin-orbit-torque (SOT) magnetoresistive random access memory (MRAM) cell stack disposed above and in electrical contact with the SHE rail, wherein the SOT-MRAM cell stack comprises a free layer, a tunnel junction layer, and a reference layer, forming a cylindrical diode structure above and in electrical contact with the SOT-MRAM cell stack, forming a write line disposed in electrical contact with the SHE rail, and forming a read line disposed above and adjacent to an outer cylindrical electrode of the diode structure.

Spin-orbit-torque magnetoresistive random-access memory with integrated diode

The embodiments herein describe a vertical field effect transistor (FET) with a gate that includes different work function metals (WFMs). Each WFM can be made up of one material (or one layer) or multiple materials forming multiple layers. In any case, the gate includes at least two different WFMs. For example, a first WFM may have a different material or layer than a second WFM in the gate, or one layer of the first WFM may have a different thickness than a corresponding layer in the second WFM. Having different WFMs in the gate can reduce the gate induced drain leakage (GIDL) in the FET.

Vertical field effect transistor with dual threshold voltage

A method of manufacturing and resultant device are directed to an inverted wide-base double magnetic tunnel junction device having both high-efficiency and high-retention arrays. The method includes a method of manufacturing, on a common stack, a high-efficiency array and a high-retention array for an inverted wide-base double magnetic tunnel junction device. The method comprises, for the high-efficiency array and the high-retention array, forming a first magnetic tunnel junction stack (MTJ2), forming a spin conducting layer on the MTJ2, and forming a second magnetic tunnel junction stack (MTJ1) on the spin conducting layer. The first magnetic tunnel junction stack for the high-retention array has a high-retention critical dimension (CD) (HRCD) that is larger than a high-efficiency CD (HECD) of the first magnetic tunnel junction stack for the high-efficiency array. The second magnetic tunnel junction stack (MTJ1) is shorted for the high-retention array and is not shorted for the high-efficiency array.

On-chip integration of a high-efficiency and a high-retention inverted wide-base double magnetic tunnel junction device

Growing community of inventors

White Plains, NY, United States of America

Pouya Hashemi