Semiconductor Manufacturing International (shanghai) Corporation

Semiconductor Manufacturing International (beijing) Corporation

Peking University

Semiconductor Manufacturing (shanghai) International Corporation

Semiconductor Manufacturing (beijing) International Corporation

Poren Tang

Ru Huang

Yimao Cai

Shiqiang Qin

Yu Jia Tang

Yue Pan

Xin Huang

Qianqian Huang

Gengyu Yang

Shenghu Tan

Semiconductor devices fabrication method is provided. The method for fabricating the semiconductor device includes: providing a semiconductor substrate; forming a gate structure on a surface of the semiconductor substrate; forming protective sidewall spacers on sidewall surfaces of the gate structure and to cover sidewall surfaces of the gate dielectric layer; forming sacrificial sidewall spacers on sidewall surfaces of the protective sidewall spacers and between the protective sidewall spacers and the gate structure; forming a first dielectric layer on the surface of the semiconductor substrate around the gate structure, the protective sidewall spacers and the sacrificial sidewall spacers; forming conductive plugs in the first dielectric layer at opposite sides of the gate structure, the protective sidewall spacers and the sacrificial sidewall spacers; and removing the sacrificial sidewall spacers to form air gap spacers between the protective sidewall spacers and the conductive plugs.

Semiconductor fabrication method and structure using multiple sacrificial layers to form sidewall spacers

The present specification discloses a semiconductor device and a method for manufacturing same. In one implementation, the method may include: providing a semiconductor structure, wherein the semiconductor structure includes a substrate, a gate structure disposed on the substrate, initial spacer layers on side surfaces of two sides of the gate structure, and a first inter-layer dielectric layer covering the gate structure and the initial spacer layers; and the substrate includes a source and a drain respectively located on the two sides of the gate structure; etching the first inter-layer dielectric layer to form a source contact hole and a drain contact hole that expose a part of the initial spacer layer; removing the exposed part of the initial spacer layer to expose the side surface of the gate structure; forming a spacer structure layer on the exposed side surface of the gate structure; forming a source contact member and a drain contact member in the contact holes; selectively removing at least a part of the spacer structure layer to form an air gap; and forming a second inter-layer dielectric layer covering the air gap. In the present invention, an air gap spacer structure can be formed and parasitic capacitance is reduced.

Semiconductor device and method for manufacturing same

This application discloses a gate-all-around field effect transistor and a method for manufacturing same. In some implementations the method may include: forming a first fin structure on a substrate, where each first fin structure includes one first laminated structure, where the first laminated structure sequentially includes a sacrificial layer, a support layer, and a channel layer from bottom to top; forming a dummy gate structure across the first fin structure, where the dummy gate structure includes a dummy gate dielectric layer, a dummy gate on the dummy gate dielectric layer, and a first spacer on a side surface of the dummy gate; removing parts of the first fin structure located on two sides of the dummy gate structure, to form a second fin structure; performing first etching on a side surface of the sacrificial layer in the second fin structure, to form a first space; forming a second spacer in the first space; performing second etching on a side surface of the channel layer in the second fin structure, to form a second space; and performing selective epitaxy on the side surface of the channel layer in the second fin structure, to form a source region and a drain region, where along a direction of a channel, compared with a side surface, distal to the sacrificial layer, of the second spacer, the side surface of the channel layer after the second etching is closer to the sacrificial layer.

Gate-all-around field effect transistor and method for manufacturing same

Semiconductor devices is provided. The semiconductor device includes a semiconductor substrate having a first region and an adjacent second region; a plurality of adjacent first fins in the first region of the semiconductor substrate; a plurality of adjacent second fins in the second region of the semiconductor substrate; a first type of fin sidewall spacers; a second type of fin sidewall spacers; first doped layers formed between adjacent first type of fin sidewall spacers in the first region; and second doped layers formed between adjacent first type of fin sidewall spacers in the second region.

Semiconductor device

Semiconductor devices and fabrication methods are provided. An exemplary fabrication method includes providing a semiconductor substrate; forming at least one gate structure having a gate dielectric layer on a surface of the semiconductor substrate; forming first sidewall spacers on a first sidewall surface region of the gate structure and covering sidewall surfaces of the gate dielectric layer; forming second sidewall spacers on a second sidewall surface region of the gate structure and top surfaces of the first sidewall spacers and made of a material different from a material of the first sidewall spacers; forming conductive plugs in the dielectric layer at both sides of the gate structure, the first sidewall spacers and the second sidewall spacers; and removing the second sidewall spacers to form air gap spacers above the first sidewall spacers and between the second sidewall surface region of the gate structure and the conductive plugs.

Semiconductor device and fabrication method including air gap spacers

Semiconductor devices and fabrication methods are provided. An exemplary fabrication method includes forming a first type of fin sidewall spacers and a second type of fin sidewall spacers. The first type of fin sidewall spacers are formed on two sidewall surfaces of a third fin portion group along a width direction of the third fin portions and two sidewall surfaces of a fourth fin portion group along a width direction of the fourth fin portions. The second type of fin sidewall spacers are formed between adjacent third fin portions and sidewall surfaces of the third fin portions and between adjacent fourth fin portions and on sidewall surfaces of the fourth fin portions. Top surfaces of the first type of fin sidewall spacers are higher than top surfaces of the second type of fin sidewall spacers and top surfaces of the third fin portions and the fourth fin portions.

Semiconductor device and fabrication method thereof

Tunnel field-effect transistors are provided. A tunnel field-effect transistor (TFET) includes a semiconductor substrate; a gate structure having a first side and an opposing second side formed on the semiconductor substrate. A first doped source/drain layer is formed in the semiconductor substrate at the first side of the gate structure. The first doped source/drain layer is doped with a first type of doping ions and a first contact interface between the first doped source/drain layer and a channel region of the semiconductor substrate has a plurality of protruding structures protruding toward the channel region under the gate structure. A second doped source/drain layer in the semiconductor substrate at the second side of the gate structure. The second doped source/drain layer is doped with a second type of doping ions having a conductive type opposite to the first source/drain doping layer.

Tunnel field-effect transistor

Tunnel field-effect transistors and fabrication methods are provided. An exemplary fabrication method includes providing a semiconductor substrate; forming a gate structure having a first side and an opposing second side on the semiconductor substrate; and forming a first doped source/drain layer in the semiconductor substrate at the first side of the gate structure. The first doped source/drain layer is doped with a first type of doping ions and a first contact interface between the first doped source/drain layer and the channel region has protruding structures protruding toward a channel region under the gate structure. The method also includes forming a second doped source/drain layer in the semiconductor substrate at the second side of the gate structure. The second doped source/drain layer is doped with a second type of doping ions having a conductivity opposite to the first doped source/drain layer.

Tunnel field-effect transistor and fabrication method thereof

Semiconductor structures and fabrication methods are provided. An exemplary fabrication method includes providing a base substrate; forming a gate structure on a top surface of the base substrate; and forming a first doped source/drain layer at both sides of the gate structure. A minimum distance between a sidewall surface of the first doped source/drain doping layer and an adjacent sidewall surface of the gate structure is a first distance. The method also includes forming a second doped source/drain layer on the first doped source/drain layer at both sides of the gate structure. A minimum distance between a sidewall surface of the second doped source/drain doping layer and an adjacent sidewall surface of the gate structure is a second distance; and the second distance is greater than the first distance.

Semiconductor structure and fabrication method thereof

The present invention discloses a method for achieving four-bit storage by using a flash memory having a splitting trench gate. The flash memory with the splitting trench gate is disclosed in a Chinese patent No. 200710105964.2. At one side that each of two trenches is contacted with a channel, a programming for electrons is achieved by using a channel hot electron injection method; and at the other side that each of the two trenches is contacted with a source or a drain, a programming for electrons is achieved by using an FN injection method, so that a function of a four-bit storage of the device is achieved by changing a programming mode. Thus, a performance of the device is improved while a storage density is greatly increased.

Method for achieving four-bit storage using flash memory having splitting trench gate

The invention provides a flash memory array structure and a method for programming the same, which relates to a technical field of nonvolatile memories in ultra large scale integrated circuit fabrication technology. The flash memory array of the present invention includes memory cells, word lines and bit lines connected to the memory cells, wherein the word lines connected to control gates of the memory cells and the bit lines connected to drain terminals of the memory cells are not perpendicular to each other but cross each other at an angle; the control gates of two memory cells adjacent to each other along the channel direction between every two bit lines are controlled by two word lines, respectively, drain terminals thereof are controlled by two bit lines, respectively, and source terminals thereof are shared. The present invention also provides a method for programming the flash memory array structure, which can realize a programming with low power consumption.

Programming method for programming flash memory array structure

The present invention discloses a flash memory and the fabrication method and the operation method for the same. The flash memory comprises two memory cells of vertical channels, wherein a lightly-doped N type (or P type) silicon is used as a substrate; a P+ region (or an N+ region) is provided on each of the both ends of the silicon surface, and two channel regions perpendicular to the surface are provided therebetween; an N+ region (or a P+ region) shared by two channels is provided over the channels; a tunneling oxide layer, a polysilicon floating gate, a block oxide layer and a polysilicon control gate are provided sequentially on the outer sides of each channel from inside to outside; and the polysilicon floating gate and the polysilicon control gate are isolated from the P+ region by a sidewall oxide layer. The whole device is a two-bit TFET type flash memory with vertical channels which has better compatibility with prior-art standard CMOS process. As compared with a conventional MOSFET-based flash memory, the flash memory according to the present invention possesses various advantages such as high programming efficiency, low power consumption, effective inhibition of punch-through effect, and high density, etc.

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Beijing, China

Poren Tang