Intel Corporation

Pooya Tadayon

Joe F Walczyk

Mark T Bohr

Chandra Mohan Jha

Weihua Tang

Robert L Sankman

Wilfred Gomes

Rajesh Kumar

Doug B Ingerly

Zhichao Zhang

David Shia

Xavier Francois Brun

Paul J Diglio

Karumbu Meyyappan

Shrenik Kothari

Tarek A Ibrahim

Zhimin Wan

Prateek J Dujari

Changhua Liu

Justin Michael Huttula

Franklin G Monzon

Chia-Pin Chiu

Kristof Darmawikarta

Srikant Nekkanty

Kyle Jordan Arrington

Liang Zhang

Eric J M Moret

David M Craig

Johanna M Swan

Adel A Elsherbini

Shawna M Liff

Srinivas V Pietambaram

Kemal Aygun

Mauro J Kobrinsky

Yonggang Li

Brandon C Marin

Leonel R Arana

Prithwish Chatterjee

Shankar Devasenathipathy

Brennen Karl Mueller

Jin Yang

Abram M Detofsky

Ting Zhong

Steven A Klein

Bai Nie

Aastha Uppal

Jin Pan

Roy Swart

Feifei Cheng

Srinivas Venkata Ramanuja Pietambaram

Benjamin Duong

Arun Krishnamoorthy

Hari Mahalingam

Prabhakar Subrahmanyam

Erkan Acar

Warren Stuart Crippen

Ying-Feng Pang

Ethan Caughey

Yi Xia

Youngseok Oh

Evan M Fledell

Rahima K Mohammed

Michael E Ryan

Victor Polyanko

Zhe Chen

Brett D Grossman

John Michael Peterson

Koorosh Zaerpoor

Mustapha Amadu Abdulai

Dinia P Kitendaugh

Andrew J Hoitink

Mark W Dryfuse

Stephen Smith

Benjamin J Norris

Armen Y Balian

Muhammad Ahmad

Tanner Schulz

A microelectronic socket structure and a method of forming the same. The socket structure comprises: a socket structure housing defining a cavity therein; and an interconnection structure including: a contact element disposed at least in part within the cavity, and configured to be electrically coupled to a corresponding microelectronic package, the contact element corresponding to one of a signal contact element or a ground contact element; and a conductive structure disposed at least in part within the cavity, electrically coupled to the contact element, and having an outer contour that is non-conformal with respect to an outer contour of the contact element.

Heterogenous socket contact for electrical and mechanical performance scaling in a microelectronic package

An electronic device comprises an electro-optical circuit package including at least photonic integrated circuit (PIC) having at least one light source and a package substrate; a printed circuit (PCB) including at least one optical connector to receive light from the at least one light source; and multiple liquid metal electrical contacts disposed between the package substrate and the PCB.

Reworkable zero-force insertion electrical optical package socket and method

Hyperchip structures and methods of fabricating hyperchips are described. In an example, an integrated circuit assembly includes a first integrated circuit chip having a device side opposite a backside. The device side includes a plurality of transistor devices and a plurality of device side contact points. The backside includes a plurality of backside contacts. A second integrated circuit chip includes a device side having a plurality of device contact points thereon. The second integrated circuit chip is on the first integrated circuit chip in a device side to device side configuration. Ones of the plurality of device contact points of the second integrated circuit chip are coupled to ones of the plurality of device contact points of the first integrated circuit chip. The second integrated circuit chip is smaller than the first integrated circuit chip from a plan view perspective.

Hyperchip

Various embodiments disclosed relate to photonic assemblies. The present disclosure includes methods for packaging a photonic assembly, including attaching a bridge die to a glass substrate, attaching an electronic integrated circuit die to the glass substrate and the bridge die, attaching a photonic integrated circuit die to the glass substrate and the bridge die, bonding a coupling adapter to the glass substrate and in situ forming a waveguide in the coupling adapted, the waveguide aligning with the photonic integrated circuit die.

Die last and waveguide last architecture for silicon photonic packaging

Embodiments disclosed herein include an electronic package. In an embodiment, the electronic package comprises a package substrate having a first surface and a second surface opposite from the first surface, and a die on the first surface of the package substrate. In an embodiment, the electronic package further comprises a socket interface on the second surface of the package substrate. In an embodiment, the socket interface comprises a first layer, wherein the first layer comprises a plurality of wells, a liquid metal within the plurality of wells, and a second layer over the plurality of wells.

Low force liquid metal interconnect solutions

Embodiments disclosed herein include semiconductor dies and methods of forming such dies. In an embodiment, the semiconductor die comprises a semiconductor substrate, an active device layer in the semiconductor substrate, where the active device layer comprises one or more transistors, an interconnect layer over a first surface of the active device layer, a first bonding layer over a surface of the semiconductor substrate, a second bonding layer secured to the first bonding layer, and a heat spreader attached to the second bonding layer.

Semiconductor device stack-up with bulk substrate material to mitigate hot spots

Integrated circuit packages may be formed having at least one optical via extending from a first surface of a package substrate to an opposing second surface of the package substrate. The at least one optical via creates an optical link between the opposing surfaces of the package substrate that enables the fabrication of a dual-sided optical multiple chip package, wherein integrated circuit devices can be attached to both surfaces of the package substrate for increased package density.

Through-substrate optical vias

Techniques and mechanisms for facilitating horizontal communication with a photonic integrated circuit (PIC) chip, and a lens structure which is optically coupled thereto. In an embodiment, a PIC chip comprises integrated circuitry, photonic waveguides, and integrated edge-oriented couplers (IECs) which are coupled to the integrated circuitry via the photonic waveguides. The PIC chip forms respective first divergent lens surfaces of the IECs, which are each at a respective terminus of a corresponding one of the photonic waveguides. A lens structure, which is adjacent to the IECs, comprises a second divergent lens surface having an orientation which is substantially orthogonal to the respective orientations of the first divergent lens surfaces. In another embodiment, an edge of the PIC chip forms one or more recess structures, and the lens structure comprises one or more tenon portions which each extends into a respective recess structure of the one or more recess structures.

Device, method and system for optical communication with a photonic integrated circuit chip and a transverse oriented lens structure

An inductor can be formed in a coreless electronic substrate from magnetic materials and/or fabrication processes that do not result in the magnetic materials leaching into plating and/or etching solutions/chemistries, and results in a unique inductor structure. This may be achieved by forming the inductors from magnetic ferrites. The formation of the electronic substrates may also include process sequences that prevent exposure of the magnetic ferrites to the plating and/or etching solutions/chemistries.

Coreless electronic substrates having embedded inductors

Embodiments include a package substrate and semiconductor packages. A package substrate includes a first cavity in a top surface, first conductive pads on a first surface of the first cavity, a second cavity in a bottom surface, second conductive pads on a second surface of the second cavity, where the first surface is above the second surface, and a third cavity in the first and second cavities, where the third cavity vertically extends from the top surface to the bottom surface. The third cavity overlaps a first portion of the first cavity and a second portion of the second cavity. The package substrate may include conductive lines coupled to the first and second conductive pads, a first die in the first cavity, a second die in the second cavity, and interconnects in the third cavity that directly couple first die to the second die.

Double-sided substrate with cavities for direct die-to-die interconnect

An apparatus is described. The apparatus includes a liquid cooling system having multiple heat-exchangers and multiple valves. The multiple valves are to enable/disable participation of individual ones of the heat-exchangers within the liquid cooling system. The apparatus includes an information keeping device to store information that correlates a number of the multiple heat exchangers to be enabled to realize one or more semiconductor chips' target temperature for a power consumption of the one or more semiconductor chips for a plurality of combinations of target temperature and power consumption. The controller is coupled to the liquid cooling system and the information keeping device to dynamically determine during runtime of a system having the one or more semiconductor chips an appropriate number of the multiple heat exchangers to enable to realize a particular target temperature for the one or more semiconductor chips for a particular power consumption of the one or more semiconductor chips, and, update the information in the information keeping device with a new correlation that correlates the appropriate number with the particular target temperature and particular power consumption.

Self cooling adaptive flow branching heat exchanger system for cooling of one or more semiconductor chips

Techniques and mechanisms for optically coupling a photonic integrated circuit (PIC) chip to an optical fiber via a planar optical waveguide structure. In an embodiment, a PIC chip comprises integrated circuitry, photonic waveguides, and integrated edge-oriented couplers (IECs) which are coupled to the integrated circuitry via the photonic waveguides. The PIC chip forms respective divergent lens surfaces of the IECs, which are each at a respective terminus of a corresponding one of the photonic waveguides. A planar optical waveguide structure, which is adjacent to the IECs, comprises a core which is optically coupled between the PIC chip and an array of optical fibers. In another embodiment, an edge of the PIC forms a stepped structure, wherein an upper portion of the stepped structure comprises the plurality of coplanar IECs, and a lower portion of the stepped structure extends past the plurality of coplanar IECs.

Device, method and system for optical communication with a waveguide structure and an integrated optical coupler of a photonic integrated circuit chip

A hybrid thermal interface material (TIM) suitable for an integrated circuit (IC) die package assembly. The hybrid TIM may include a heat-spreading material having a high planar thermal conductivity, and a supplemental material having a high perpendicular thermal conductivity at least partially filling through-holes within the heat-spreading material. The hybrid TIM may offer a reduced effective spreading and vertical thermal resistance. The heat-spreading material may have high compressibility (low bulk modulus or low hardness), such as a carbon-based (e.g., graphitic) material. The supplemental material may be of a suitable composition for filling the through-hole. The heat-spreading material, once compressed by a force applied through an IC die package assembly, may have a thickness substantially the same as that of the supplemental material such that both materials make contact with the IC die package and a thermal solution.

Hybrid thermal interface material (TIM) with reduced 3D thermal resistance

Embodiments disclosed herein include a temperature control system. In an embodiment, the temperature control system comprises a fluid reservoir for holding a fluid, and a spray chamber fluidically coupled to the fluid reservoir. In an embodiment, a pump is between the spray chamber and the fluid reservoir, where the pump provides the fluid to the spray chamber. In an embodiment, the temperature control system further comprises, a plurality of fluid lines between the pump and the spray chamber, where individual ones of the plurality of fluid lines are configured to provide the fluid to the spray chamber. In an embodiment, the temperature control system further comprises, a vacuum source fluidically coupled to the spray chamber, where the vacuum source controls a pressure within the spray chamber.

Vacuum modulated two phase cooling loop efficiency and parallelism enhancement

Growing community of inventors

Portland, OR, United States of America

Pooya Tadayon