United Microelectronics Corp.

Pong-Wey Huang

Chan-Lon Yang

Wei-Hsin Liu

Chun-Yao Yang

Bor-Shyang Liao

Jen-Po Huang

Chang-Hung Kung

Ya-Hsueh Hsieh

Teng-Chun Hsuan

Shuen-Cheng Lei

Hsi-Hua Liu

Chia-Jen Wang

Huai-Te Huang

A semiconductor process includes the following steps. An interdielectric layer is formed on a substrate and the interdielectric layer has a first recess and a second recess. A metal layer is formed to cover the surface of the interdielectric layer, the first recess and the second recess. Partially fills a sacrificed material into the first recess and the second recess so that a portion of the metal layer in each of the recesses is respectively covered. The uncovered metal layer in each of the recesses is removed. The sacrificed material is removed. An etching process is performed to remove the remaining metal layer in the first recess and reserve the remaining metal layer in the second recess.

Semiconductor process

A method for optimizing an inspection recipe of a defect inspection tool is described. A substrate having thereon intentional defects and locating patterns beside the intentional defects is provided. The defect inspection tool is used to detect the intentional defects with an inspection recipe and obtain the distribution of undetected or partially detected intentional defects. The locating patterns are utilized to locate the undetected or partially detected intentional defects and thereby determine the type(s) of the undetected or partially detected intentional defects. The inspection recipe is modified according to the type(s) of the undetected or partially detected intentional defects in a manner such that there is a minimal number of undetected or partially detected intentional defects under the inspection of the defect inspection tool.

Method and pattern carrier for optimizing inspection recipe of defect inspection tool

Growing community of inventors

Tainan, Taiwan

Pong-Wey Huang