International Business Machines Corporation

Pong-Fei Lu

Yuen H Chan

William Robert Reohr

Jente Benedict Kuang

Tze-Chiang Chen

Bernard S Meyerson

Denny D Tang

Mary Joseph Saccamango

Yuan-Chen Sun

David Howard Allen

Jae-Joon Kim

Ching-Te Kent Chuang

Daniel Lawrence Stasiak

Antonio R Pelella

Rahul M Rao

James H Comfort

Saibal Mukhopadhyay

Tae-Hyoung Kim

Shao-yi Wang

Janes H Comfort

A ring oscillator has an odd number of NOR-gates greater than or equal to three, each with first and second input terminals, a voltage supply terminal, and an output terminal. The first input terminals of all the NOR-gates are interconnected, and each of the NOR-gates has its output terminal connected to the second input terminal of an immediately adjacent one of the NOR-gates. During a stress mode, a voltage supply and control block applies a stress enable signal to the interconnected first input terminals, and an increased supply voltage to the voltage supply terminals. During a measurement mode, this block grounds the interconnected first input terminals, and applies a normal supply voltage to the voltage supply terminals. Also included are an analogous NAND-gate based circuit, a circuit combining the NAND- and NOR-aspects, a circuit with a ring oscillator where the inverters may be coupled directly or through inverting paths, and circuits for measuring the bias temperature instability effect in pass gates.

Circuits and design structures for monitoring NBTI (negative bias temperature instability) effect and/or PBTI (positive bias temperature instability) effect

A method and apparatus are provided for implementing enhanced silicon-on-insulator (SOI) passgate operations. The apparatus for implementing enhanced silicon-on-insulator (SOI) passgate operations includes a silicon-on-insulator (SOI) passgate field effect transistor. A select input is coupled to the silicon-on-insulator (SOI) passgate field effect transistor. A discharging field effect transistor of an opposite channel type is coupled to the silicon-on-insulator (SOI) passgate field effect transistor. The discharging field effect transistor is activated during an off cycle of the silicon-on-insulator (SOI) passgate field effect transistor. The discharging field effect transistor is coupled to the body of the SOI passgate field effect transistor. The discharging field effect transistor is deactivated during an on cycle of the SOI passgate field effect transistor, whereby the body of the SOI passgate field effect transistor floats during the on cycle. The method for implementing enhanced silicon-on-insulator (SOI) passgate operations can be used with N-channel or P-channel implementations as well as with a combination of N-channel and P-channel devices.

Method and apparatus for enhanced SOI passgate operations

In a method and apparatus for reducing parasitic bipolar current in an insulated body, field effect transistor (&ldquo;FET&rdquo;), for an n-type FET, the body of the insulated body NFET is electrically isolated, responsive to turning on the NFET. This permits a charge to accumulate on the body in connection with turning the NFET on, temporarily lowering the threshold voltage for the insulated body NFET. Responsive to turning off the insulated body NFET, at least a portion of the charge on the body is discharged. This discharging of the body reduces parasitic bipolar current which would otherwise occur upon turning the NFET back on if the body had charged up during the time when the NFET was off. For a p-type FET that is susceptible to parasitic bipolar current, the body is discharged responsive to turning off the PFET, and isolated responsive to turning on the PFET.

Method and apparatus for reducing parasitic bipolar current in a silicon-on-insulator transistor

A memory and sense amplifier with latched output included therein derives high speed and noise immunity with precharged logic circuits through the separation of sense amplifier enablement and resetting by use of the precharge operation. Inclusion of bit line decoders which are wholly or partially self-resetting and self-precharging in sense amplifier support circuitry allows high performance at extremely short memory operation cycle times. A multiplexor is included which is usable in operating cycles as well as test cycles of the memory and further, in combination with other elements of the memory and sense amplifier arrangement, enables the pipelining of plural memory operations in a single memory cycle.

Precharged bit decoder and sense amplifier with integrated latch usable

A pipelined set-associative cache data READ/WRITE access circuit advancing the processing performance speeds in microprocessor memories. It provides an apparatus and method to obtain quick access to multi-way cache memory associates for both READ and WRITE operations satisfying the required increased memory access performance speeds for modern microprocessor utilizations. Special methodology is employed to minimize the number of pathways and the pathway through-time of the longest time critical path even with a provision of array built in self test (ABIST) capability.

Set-select multiplexer with an array built-in self-test feature

This invention relates to a bipolar transistor which incorporates, in a raised base regime, an emitter, collector pedestal and intrinsic and extrinsic bases all of which are self-aligned. The invention also relates to a process for fabricating such devices which obtains the self-alignment of the above mentioned elements using a single lithographic and masking step. The structure of the transistor, in addition to having the self-aligned elements, incorporates a composite dielectric isolation layer which not only permits the carrying out of a number of functions during device fabrication but also provides for desired electrical characteristics during device operation. The composite isolation layer consists of an oxide layer adjacent the semiconductor surface; a nitride layer on the oxide layer and an oxide layer on the nitride layer in the final structure of the device. The last mentioned oxide layer starts out early in the fabrication process as a layer of oxidizable material, preferable polycrystalline silicon, which, at later steps in the process, acts as an etch-stop in its unoxidized state and as a memory element and mask in its oxidized state when a self-aligned datum element is removed and the thus exposed underlying dielectric elements must be removed to provide a planar emitter opening. The resulting transistor includes a planar emitter-emitter contact interface which provides for fine control of emitter depth in the underlying intrinsic base region.

Low capacitance bipolar junction transistor and fabrication process

This invention relates to a bipolar transistor which incorporates, in a raised base regime, an emitter, collector pedestal and intrinsic and extrinsic bases all of which are self-aligned. The invention also relates to a process for fabricating such devices which obtains the self-alignment of the above mentioned elements using a single lithographic and masking step. The structure of the transistor, in addition to having the self-algined elements, incorporates a composite dielectric isolation layer which not only permits the carrying out of a number of functions during device fabrication but also provides for desired electrical characteristics during device operation. The composite isolation layer consists of an oxide layer adjacent the semiconductor surface; a nitride layer on the oxide layer and an oxide layer on the nitride layer in the final structure of the device. The last mentioned oxide layer starts out early in the fabrication process as a layer of oxidizable material, preferably polycrystalline silicon, which, at later steps in the process, acts as an etch-stop in its unoxidized state and as a memory element and mask in its oxidized state when a self-aligned datum element is removed and the thus exposed underlying dielectric elements must be removed to provide a planar emitter opening. The resulting transistor includes a planar emitter-emitter contact interface which provides for fine control of emitter depth in the underlying intrinsic base region.

Process for fabricating low capacitance bipolar junction transistor

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Yorktown Heights, NY, United States of America

Pong-Fei Lu