Chartered Semiconductor Manufacturing Ltd (corporation)

Poh Suan Tan

Lap Chan

Che-Chia Wei

Chock Hing Gan

Qinghua Zhong

Bob Hsino-Lun Lee

Gang Qian

Qian Gang

Lap Hung Chan

A method for fabricating an anti-fuse cell using an undoped polysilicon film as a mask in defining the anti-fuse window is described. A layer of silicon oxide is provided over the surface of a semiconductor substrate. A first undoped polysilicon layer is deposited overlying the silicon oxide layer. The first undoped polysilicon layer is covered with a photoresist layer patterned to form a mask. The first undoped polysilicon layer and a portion of the silicon oxide layer are etched away where they are not covered by the mask to form a cell opening. The mask and the remaining silicon oxide within the cell opening are removed. An insulating layer is deposited over the surface of the first undoped polysilicon layer and within the cell opening. A second polysilicon layer is deposited overlying the insulating layer and doped. The second polysilicon layer is patterned to form an anti-fuse cell. Gate electrodes and source and drain regions are formed completing the fabrication of the integrated circuit device.

Definition of anti-fuse cell for programmable gate array application

A method is described for filling trenches with dielectric for shallow trench isolation which completely fills the trench and avoids problems due to dishing at the top of the trench. A trench is formed in a substrate having a second dielectric material formed thereon. The trench is lined with a third dielectric material. Sub atmospheric chemical vapor deposition, SACVD, of tetra-ethyl-ortho-silicate and ozone is used to grow a fourth dielectric on the surface of the second dielectric material and in the trench lined with the third dielectric material. The growth rate of fourth dielectric on the third dielectric is greater than the growth rate of the fourth dielectric on the second dielectric using SACVD of tetra-ethyl-ortho-silicate and ozone. The difference in growth rate assures that the trench is completely filled with fourth dielectric even for relatively thin layers of fourth dielectric grown on the second dielectric. This provides good planarity for a planarized substrate and avoids the problem of dishing at the top of the trench.

Method to avoid dishing in forming trenches for shallow trench isolation

A method was achieved for fabricating field oxide regions (shallow trench isolation) having raised portions which are self-aligned and extend over edges of device areas. This results in FETs with improved sub-threshold characteristics and lower sub-threshold leakage currents. The method consists of forming a pad oxide and depositing a doped polysilicon layer and a hard mask layer on a silicon substrate. Shallow trenches are etched through the hard mask, doped polysilicon layer and partially into the silicon substrate. A thermal oxidation is used to form a liner oxide in the trenches and to oxidize, at a higher oxidation rate, the sidewalls of the doped polysilicon layer to form an oxide over the edges of the device areas. A gap-fill oxide is deposited in the trenches and chemical mechanical polished (CMP) back to the polysilicon layer. The remaining polysilicon layer over the device areas is selectively removed to provide a field oxide having raised portions formed over the edges of the device areas. This eliminates the wrap-around corner effect which in the prior art resulted in enhanced corner conduction and increased sub-threshold leakage currents at substrate back bias. This improved method also provides greater processing latitude during the chemical mechanical polish step.

Method for making improved shallow trench isolation for semiconductor

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Singapore, Singapore

Poh Suan Tan