Intel Corporation

Pochang Hsu

Jun Shi

Animesh Mishra

Don J Nguyen

Erik De La Iglesia

John William Horigan

Robert T Jackson

Siripong Sritanyaratana

Rajendra M Abhyankar

David Wyatt

James P Kardach

Kristoffer Fleming

Gunner D Danneels

Jeffrey L Huckins

Richard Keith Dodge

Uma M Gadamsetty

Brian V Belmont

Sandeep K Jain

Richard A Forand

Ravi Nagaraj

Venu Madhav Kuchibhotla

Systems and methods of managing memory devices provide for reduced power consumption and better thermal management through enhanced memory throttling. In one embodiment a memory unit includes a memory device and a temperature measurement module coupled to the memory device. The temperature measurement device measures the internal temperature of the memory device. Memory throttling can therefore be implemented based on more accurate measurements and with a much shorter response time.

Throttling memory in response to an internal temperature of a memory device

Throttling memory in a computer system

A computer system having one or more components capable of being in either wake or sleep states includes a power manager and a voltage regulator. The power manager may generate a power state signal indicating the power state of the component, and this signal may be provided to the voltage regulator. The voltage regulator may supply power to the component. The target voltage level of the power may be dependent on both a current level of the power and the power state signal.

Method and apparatus for reducing the power consumed by a computer system

A thermal management system is described which may be implemented on a semiconductor die. The system may include a thermal sensor thermally coupled to the die to sense the temperature of the die and generate an output representing the sensed temperature, and an adjustable compensation circuit coupled to the thermal sensor to compensate the thermal sensor output. The adjustable compensation circuit may be applied to the thermal sensor or to a threshold.

Calibration of thermal sensors for semiconductor dies

An embodiment of the present invention is a technique to provide a reconfigurable repair circuit in a memory device. A table structure contains a plurality of entries, each entry having a defective address word and a redundant address word. The redundant address word corresponds to a redundant block and is generated in response to a memory access to a defective input/output (I/O) line in a memory block of the memory device. A decoding circuit decodes the redundant address word to select a redundant I/O line in the redundant block to replace the defective I/O line.

Reconfigurable memory block redundancy to repair defective input/output lines

A method and apparatus for a user to interface with a mobile computing device is disclosed. In one embodiment, a method, comprises providing information on a user interface connected to a mobile computing device having a primary display, wherein the mobile computing device can be operated in multiple power states, and the user interface does not include the primary display

Method and apparatus for a user to interface with a mobile computing device

A computer system includes a voltage regulator that supplies power to a component. The component may provide a signal indicating an amount of current the component consumes under a high utilization operating condition. The voltage regulator may then determine the slope of a load line using this signal.

Method and apparatus for configuring a voltage regulator based on current information

The present invention relates to an error correction and selective inversion circuit (ESIC). The ESIC includes a power-on logic state (POLS) bus having a data signal and an error code correction (ECC) generator having an input coupled to the POLS bus. The ECC generator includes one or more correction pins. The ESIC also includes an inversion generator having an input attached to the POLS bus in parallel with the ECC generator. The output of the inversion generator is integrated with the output of on or more correction pins from the ECC generator so as to form an inverted data signal output. An inverted data signal is recovered by the ESIC in an inversion recovery.

Bus power savings using selective inversion in an ECC system

A dual mode I/O interface circuit compatible with either GTL logic signals or traditional CMOS logic signals comprises a connection node with a differential sense amplifier having one input coupled to the connection node, and the other input coupled to a reference voltage. Pull-up and pull-down circuits are coupled to the connection node. Logic circuitry is coupled to the gate of the at least one P-type field-effect transistor of the pull-up circuit, and the gate of the at least one N-type field-effect transistor of the pull-down circuit to control the conductivity of the field-effect transistors. In this manner, a first representation of the input signal compatible with GTL logic signals as provided at the connection node when the mode signal is asserted, and a second representation of the input signal compatible with CMOS logic levels as provided at the connection node when the mode signal is deasserted.

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Fremont, CA, United States of America

Pochang Hsu