Vanguard International Semiconductor Corporation

Po-Yuan Tang

Jian-Yuan Hsiao

Hsuan-Chi Su

Yang-Sen Yeh

Wei-Ting Chen

Chih-Chuan Ke

Yu-Chuan Chang

Yi-Ling Hung

Feng-Chih Kuo

A level shifter receives an input signal through an input terminal and converts the input signal to an output signal. The level shifter includes an input stage circuit and an output stage circuit. The input stage circuit receives the input signal. The input stage circuit includes an N-type transistor that has a gate coupled to the input terminal, a drain coupled to a first node, a source coupled to a ground, and a bulk connected to the source. The output stage circuit is coupled to an output terminal and the first node. The output stage circuit includes a P-type transistor that has a gate, a source coupled to the supply terminal, a drain coupled to the first node, and a bulk disconnected from the source. The output signal is generated at the output terminal. An inverted output signal is generated at the first node.

Level shifter

A sensing amplifier circuit includes first and second P-type transistors and first and second N-type transistors. The first P-type transistor includes a gate coupled to an input node, a source and a bulk coupled to a first node, and a drain coupled to an output node. The second P-type transistor includes a gate coupled to an inverted reading-triggered signal, a source coupled to a voltage source, and a drain coupled to the first node. The first N-type transistor includes a gate coupled to the input node, a drain coupled to the output node, and a source coupled to ground. The second N-type transistor includes a gate receiving the inverted reading-triggered signal, a drain coupled to the output node, and a source coupled to the ground. The first P-type transistor includes an N-type well region that is electrically connected to the source and bulk of the first P-type transistor.

Sensing amplifier circuit and memory device

A non-volatile memory device includes a set of memory cells, a cycle transistor, a reference transistor and a control circuit. The control circuit is coupled to the set of memory cells, the cycle transistor and the reference transistor. A method of controlling the non-volatile memory device includes in a program operation or an erase operation of the set of memory cells, the control circuit determining a state of the cycle transistor, and upon determining the cycle transistor being in an erased state (or a programmed state), the control circuit setting the reference transistor from a reference state to the erased state (or the programmed state), and then restoring the reference transistor from the erased state (or the programmed state) to the reference state. The reference state is set between the erased state and a programmed state.

Non-volatile memory device for mitigating cycling trapped effect and control method thereof

A memory device and a control method for the memory device are provided. When it is determined that a bit read from a memory cell in a memory cell array is an erroneous bit, the memory device triggers a second reading cycle. During the second reading cycle, if the bit read from the same memory cell is still an erroneous bit, the memory cell is deemed to be a real defective memory cell. At this time, a repairing memory cell is selected from a repairing memory cell array to replace the real defective memory cell. The selected repairing memory cell and the real defective memory cell are coupled to the same word line.

Memory device and control method for memory device

A storage device including a cell array and a disturb-free circuit is provided. The cell array includes a first cell and a second cell. The first cell is coupled to a first conductive line and a specific conductive line. The second cell is coupled to a second conductive line and the specific conductive line. The disturb-free circuit performs a first write operation on the first cell and performs a verification operation on the second cell. The verification operation determines whether data stored in the second cell is disturbed by the first write operation. In response to the data stored in the second cell being disturbed by the first write operation, the disturb-free circuit performs a second write operation.

Storage device and control method thereof

A test circuit testing a storage circuit and including a controller, a pattern-generator circuit, a comparing circuit, and a first register is provided. The storage circuit includes a storage block. The controller is configured to generate a plurality of internal test signals. The pattern-generator circuit generates and provides test data to the storage circuit according to the internal test signal. The storage circuit writes the test data into the storage block and reads the storage block to generate read data. The comparing circuit compares the test data and the read data to generate a test result. The first register stores the test result. The controller determines whether the storage circuit is working normally according to the test result stored in the first register.

Test circuit for testing a storage circuit

An access method for a memory device is provided. The access method includes receiving external data; reading a plurality of first memory cells of the memory device according to a write address to obtain first original data; comparing the external data and the first original data to determine whether the number of specific cells among the first memory cells is higher than a predetermined value, wherein the value of each of the specific cells would be changed from a first value to a second value in response to the external data being written into the first memory cells; and reversing the external data to generate reversed data and writing the reversed data into the first memory cells to replace the first original data in response to the number of specific cells being higher than the predetermined value.

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Hsinchu, Taiwan

Po-Yuan Tang