Taiwan Semiconductor Manufacturing Comp. Ltd.

Hon Hai Precision Industry Co., Ltd.

Nanning Fugui Precision Industrial Co., Ltd.

Shenzhen Fugui Precision Ind. Co., Ltd.

Po-Yu Lin

Wei-Yang Lee

Chia-Pin Lin

Tzu-Hua Chiu

Chao-Chien Lee

Teng-Chun Tsai

Kuo-Yin Lin

Wei-Han Fan

Kuan-Hao Cheng

Chun-Chieh Wang

Huai-Tei Yang

Hsien-Ming Lee

Yueh-Ching Pai

Yi-Ting Wang

Tsung-Ta Tang

Chi-Yu Chou

Chi-Jen Yang

Wei-Min Liu

LI-Li Su

Chiu-Yi Wu

Yee-Chia Yeo

Tai-Cherng Yu

Yuan-Ching Peng

Wei Hao Lu

Chien-Hui Lin

Ting-Hung Su

Ping-Yuan Lin

A semiconductor device structure is provided. The semiconductor device structure includes a substrate having a base and a fin over the base. The semiconductor device structure includes a gate stack over a top portion of the fin. The semiconductor device structure includes a first nanostructure over the fin and passing through the gate stack. The semiconductor device structure includes a second nanostructure over the first nanostructure and passing through the gate stack. The first nanostructure is thicker than the second nanostructure. The semiconductor device structure includes a stressor structure over the fin and connected to the first nanostructure and the second nanostructure.

Semiconductor device structure and method for forming the same

A semiconductor device includes a source/drain feature over a semiconductor substrate, channel layers over the semiconductor substrate and connected to the source/drain feature, a gate portion between vertically adjacent channel layers, and an inner spacer between the source/drain feature and the gate portion and between adjacent channel layers. The semiconductor device further includes an air gap between the inner spacer and the source/drain feature.

Epitaxial structures exposed in airgaps for semiconductor devices

A semiconductor device includes a source/drain feature over a semiconductor substrate, channel layers connected to the source/drain feature, a gate structure between adjacent channel layers and wrapping the channel layers, and an inner spacer between the source/drain feature and the gate structure and between adjacent channel layers. The source/drain feature has a first interface with a first channel layer of the channel layer. The first interface has a convex profile protruding towards the first channel layer.

Devices with improved operational current and reduced leakage current

Multi-gate devices and methods for fabricating such are disclosed herein. An exemplary method includes forming a semiconductor stack on a substrate, wherein the semiconductor stack includes a first semiconductor layers and a second semiconductor layers alternatively disposed, the first semiconductor layers and the second semiconductor layers being different in composition; patterning the semiconductor stack to form a semiconductor fin; forming a dielectric fin next to the semiconductor fin; forming a first gate stack on the semiconductor fin and the dielectric fin; etching to a portion of the semiconductor fin within a source/drain region, resulting in a source/drain recess; and epitaxially growing a source/drain feature in the source/drain recess, defining an airgap spanning between a sidewall of the source/drain feature and a sidewall of the dielectric fin.

Source and drain engineering process for multigate devices

The present disclosure relates to a semiconductor device and a manufacturing method of fabricating a semiconductor structure. The method includes forming an opening in a substrate and depositing a conformal metal layer in the opening. The depositing includes performing one or more deposition cycles. The deposition includes flowing a first precursor into a deposition chamber and purging the deposition chamber to remove at least a portion of the first precursor. The method also includes flowing a second precursor into the deposition chamber to form a sublayer of the conformal metal layer and purging the deposition chamber to remove at least a portion of the second precursor. The method further includes performing a metallic halide etching (MHE) process that includes flowing a third precursor into the deposition chamber.

Formation and in-situ etching processes for metal layers

A semiconductor structure is provided. The semiconductor structure includes a first nanostructure stacked over and spaced apart from a second nanostructure, a gate stack wrapping around the first nanostructure and the second nanostructure, a source/drain feature adjoining the first nanostructure and the second nanostructure, and a first inner spacer layer interposing the gate stack and the source/drain feature and interposing the first nanostructure and the second nanostructure. A dopant in the source/drain feature has a first concentration at an interface between the first inner spacer layer and the source/drain feature and a second concentration at a first distance away from the interface. The first concentration is higher than the second concentration.

Semiconductor structure and method for forming the same

A method providing guidance to a vehicle for parking includes: obtaining information of potential parking space. Information of the parking space includes likelihood of finding unoccupied parking space and navigating to the parking space according to the information of parking space. The information of the parking space guides a driver to quickly find the parking space, thereby reducing parking time, improving parking space utilization, and efficiency of road traffic management. Calculating the likelihood of finding an unoccupied space is of great assistance to a driver.

Method for guiding vehicle to park, electronic equipment, and non-transitory storage medium

A method includes providing a semiconductor substrate having first and second regions that are doped with first and second dopants respectively. The first and second dopants are of opposite types. The method further includes epitaxially growing a first semiconductor layer that is doped with a third dopant. The first and third dopants are of opposite types. The method further includes depositing a dielectric hard mask (HM) layer over the first semiconductor layer; patterning the dielectric HM layer to have an opening over the first region; extending the opening towards the semiconductor substrate; and epitaxially growing a second semiconductor layer in the opening. The second semiconductor layer is doped with a fourth dopant. The first and fourth dopants are of a same type. The method further includes removing the dielectric HM layer; and performing a first CMP process to planarize both the first and second semiconductor layers.

Method and structure for FinFET devices

A virtual cinema interactive system includes a server and at least two user terminals. The user terminals communicate with the server. An host can invite his friends to watch film together on a virtual cinema displayed on each user terminal, and distribution of virtual cinema seating, talking between film watchers, and film watcher reactions to the film can be recognized and facilitated. A virtual cinema interactive method is also disclosed.

Interactive system for virtual cinema and method

A virtual cinema interactive system includes a server and at least two user terminals. The user terminals communicate with the server. An inviter can invite his friends to watch film together on a virtual cinema displayed on each user terminal, and distribution of virtual cinema seating, talking between film watchers, and film watcher reactions to the film can be recognized and facilitated. A virtual cinema interactive method is also disclosed.

Growing community of inventors

New Taipei, Taiwan

Po-Yu Lin