Taiwan Semiconductor Manufacturing Comp. Ltd.

Mediatek Corporation

Tsinghua University

Institute for Information Industry

Po-Yu Chen

Jing-Ying Chen

Wan-Hua Huang

Kuo-Ming Wu

Chih-Hsiang Hsiao

Nan-Hsin Tseng

Chi-Hsuan Lin

Wen-Tsuen Chen

Ping-Han Tsai

Chih-Sheng Hou

Po-Hsiang Huang

Chien-Hung Lin

Fong-Yuan Chang

Wei-Chung Wang

Chih-wei Chang

Pei-Kuei Tsung

Yu-Chee Tseng

Yao-Sheng Wang

Hua Wu

Jyh Chwen Frank Lee

Jing-Fung Chen

Ching-Yi Lin

Po-Chi Sung

Jen-Chieh Yang

Sheng-Po Kuo

Yi-Ping You

Wei-Hao Kao

Huai-Ting Li

Zheng-Yong Lu

Yu-Liang Yeh

Je-Wei Liu

Yi-Min Guo

Hsien-Kai Kuo

Shou-Yao Tseng

A method includes: receiving a layout of an integrated circuit; identifying, based on the layout, at least a first net and at least a second net, wherein the first net extends through the integrated circuit along a vertical direction, and the second net terminates at a middle portion of the integrated circuit along the vertical direction; dividing the integrated circuit into a plurality of grid units, wherein the first net is constituted by a first subset of the plurality of grid units, and the second net is constituted by a second subset of the plurality of grid units; estimating a first thermal conductivity of each of the first subsets of grid units; estimating a second thermal conductivity of each of the second subsets of grid units; and estimating an equivalent thermal conductivity of the integrated circuit based on combining the first thermal conductivity and the second thermal conductivity.

Systems and methods of estimating thermal properties of semiconductor devices

A device includes a first buried layer over a substrate, a second buried layer over the first buried layer, a first well over the first buried layer and the second buried layer, a first high voltage well, a second high voltage well and a third high voltage well extending through the first well, wherein the second high voltage well is between the first high voltage well and the third high voltage well, a first drain/source region in the first high voltage well, a first gate electrode over the first well, a second drain/source region in the second high voltage well and a first isolation region in the second high voltage well, and between the second drain/source region and the first gate electrode, wherein a bottom of the first isolation region is lower than a bottom of the second drain/source region.

High voltage transistor structure

Floating-point numbers are compressed for neural network computations. A compressor receives multiple operands, each operand having a floating-point representation of a sign bit, an exponent, and a fraction. The compressor re-orders the operands into a first sequence of consecutive sign bits, a second sequence of consecutive exponents, and a third sequence of consecutive fractions. The compressor then compresses the first sequence, the second sequence, and the third sequence to remove at least duplicate exponents. As a result, the compressor can losslessly generate a compressed data sequence.

Compression of floating-point numbers for neural networks

A method of manufacturing a semiconductor device includes forming a gate structure over an active region of a substrate, the gate structure comprising a first section and a second section. The first section and the second section dividing the active region into a first source/drain region between the first section and the second section, and a pair of second source/drain regions arranged on opposite sides of the gate structure. The method further includes forming a conductive field plate over the substrate, the field plate extending between the first section and the second section and overlapping an edge of the active region. The method further includes implanting a first well in the substrate, wherein the first well overlaps the edge of the active region. The method further includes forming an isolation structure in the substrate, wherein the conductive field plate extends over the isolation structure.

Method of manufacturing a semiconductor device having a conductive field plate and a first well

A device includes a sensor configured to provide a temperature-sensitive voltage and an oscillator. The sensor includes: a first transistor, being a diode-connected transistor; a second transistor coupled between a source of the first transistor and ground, wherein a gate of the second transistor is controllable by an enable signal; and a current source configured to control the first transistor and comprising a third transistor, a drain of which is directly connected to a drain of the first transistor, the third transistor being a diode-connected transistor. The oscillator includes: a digital delay cell; and an adjustment device configured to, based on the temperature-sensitive voltage, adjust a delay of the digital delay cell. The digital delay cell produces, based on the adjusted delay, a signal at an oscillation frequency.

Device and method of operating the same

A lateral trench MOSFET comprises an insulating layer buried in a substrate, a body region in the substrate, an isolation region in the substrate, a first drain/source region over the body region, a second drain/source region in the substrate, wherein the first drain/source region and the second drain/source region are on opposing sides of the isolation region, a drift region comprising a first drift region of a first doping density formed between the second drain/source region and the insulating layer, wherein the first drift region comprises an upper portion surrounded by isolation regions and a lower portion and a second drift region of a second doping density formed between the isolation region and the insulating layer, wherein a height of the second drift region is equal to a height of the lower portion of the first drift region.

Lateral MOSFET with dielectric isolation trench

A device includes a sensor and an oscillator. The sensor provides a temperature-sensitive voltage. The oscillator includes a digital delay cell and an adjustment device. The adjustment device, based on the temperature-sensitive voltage, adjusts a delay of the digital delay cell, wherein the digital delay cell produces, based on the adjusted delay, a signal at an oscillation frequency.

A system performs convolution operations based on an analysis of the input size. The input includes data elements and filter weights. The system includes multiple processing elements. Each processing element includes multipliers and adders, with more of the adders than the multipliers. According to at least the analysis result which indicates whether the input size matches a predetermined size, the system is operative to select a first mode or a second mode. In the first mode, a greater number of the adders than the multipliers are enabled for each processing element to multiply transformed input and to perform an inverse transformation. In the second mode, an equal number of the adders and the multipliers are enabled for each processing element to multiply-and-accumulate the input. One or more of the multipliers are shared by the first mode and the second mode.

Hybrid non-uniform convolution transform engine for deep learning applications

A semiconductor device includes a substrate having an active region, a drain region in the active region, a source region in the active region, a gate structure, and a conductive field plate. The gate structure extends in a first direction over the active region. The gate structure is arranged between the drain region and the source region in a second direction transverse to the first direction. The conductive field plate extends in the second direction over an edge of the active region.

Semiconductor device having conductive feature overlapping an edge of an active region

An integrated circuit includes a circuit unit and an oscillating signal-generating assembly. The circuit unit includes a plurality of first cells. The oscillating signal-generating assembly is configured to generate different oscillating signals and includes a ring oscillator, a signal line, and a switching unit. The ring oscillator includes a plurality of second cells, each of which has an output terminal. The second cells are of the same type as the first cells. The signal line is configured to receive the different oscillating signals. The switching unit is coupled between the ring oscillator and the signal line and is configured to selectively couple the output terminals of the second cells to the signal line. A timing characteristic of a cell of the same type as the first cells can be estimated from the different oscillating signals.

Integrated circuit with an oscillating signal-generating assembly

A device comprises a buried layer over a substrate, a first well over the buried layer, a first high voltage region and a second high voltage region extending through the first well, a first drain/source region in the first high voltage region, a first gate electrode over the first well, a first spacer on a first side of the first gate electrode, wherein the first spacer is between the first drain/source region and the first gate electrode, a second spacer on a second side of the first gate electrode, a second drain/source region in the second high voltage region and a first isolation region in the second high voltage region and between the second drain/source region and the first gate electrode.

High voltage transistor structure and method

An electronic device includes an application processor and a sensor hub, where the application processor is arranged for executing applications running on a system of the electronic device, and the sensor hub is arranged for obtaining and processing sensed data from a plurality of sensors within the electronic device. In addition, the application processor further downloads location data from a remote device via a network module, and at least a portion of the downloaded location data is further stored in a storage unit of the sensor hub to be reused for positioning.

Method for performing positioning operation and associated electronic device

A stress measurement method is provided of the present disclosure. The stress measurement method includes an image capturing procedure, a phase shift calculation procedure, an isochromatic intensifying procedure and a transformation procedure. The image capturing procedure is used to capture four light intensity images with four different phase angles of a sample. The phase shift calculation procedure is used to obtain an isochromatic retardation of the sample when the four light intensity images have sufficient light intensity values. The isochromatic intensifying procedure is used to calculate two enhanced light intensity values, the background of intensified isochromatic light intensity value and the amplitude of intensified isochromatic light intensity value to obtain an isochromatic retardation when the sample is in a low stress condition. The transformation procedure is used to transform the isochromatic retardation to a stress value of the sample.

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Baoshan, China

Po-Yu Chen