Foci Fiber Optic Communications, Inc.

Powerchip Semiconductor Manufacturing Corporation

Industrial Technology Research Institute

Po-Yi Wu

Ting-Ta Hu

Shih-Ping Lee

Hsu-Liang Hsiao

Shyng-Yeuan Che

Hsiao-Pei Lin

Kuo-Fang Huang

Chieh-Yu Fang

Ting-Yan Lin

Bo-An Tsai

Yu-An Chen

Ming-Shan Deng

Shih-Siang Chen

Yi-Nung Lin

Chen-Tso Han

Chia-Kuo Chen

The present invention provides an optical interposer for chip connection including a first total internal reflective layer, a waveguide and a second total internal reflective layer. The optical interposer is disposed above a first photonic integrated circuit chip and a second photonic integrated circuit chip, coupling with the first photonic integrated circuit chip and the second photonic integrated circuit chip. The refractive indices of the first total internal reflective layer and the second total internal reflective layer are lower than the waveguide, making a light signal perform repetitive total internal reflections at the junctions between materials and advance in a zigzag shape within the waveguide, and further transmit between the first photonic integrated circuit chip and the second photonic integrated circuit chip.

Optical interposer for chip connection

The present invention provides a semiconductor structure including a substrate, a metal reflective layer, a UV glue layer, and an element. The metal reflective layer is placed on the surface of the substrate, and the UV glue layer is placed on the surface of the metal reflective layer. The element is manufactured by light-transparent material. The UV glue layer adheres the element to the metal reflective layer. By so, in the light-curing process, the curing of the UV glue is accelerated due to the metal reflective layer reflecting an ultraviolet ray.

Semiconductor structure

A pluggable optical packaging structure is provided, including: a substrate, a carrier ring, at least one optical connection assembly and a cover plate; the substrate includes at least one electronic integrated circuit (EIC) and at least one photonic integrated circuit (PIC); the carrier ring is located on the substrate, and the EIC and PIC are enclosed by the carrier ring; the optical connection assembly includes at least one socket, at least one connector, a plurality of optical fibers and at least one optical fiber array connector, the socket is located in a partial section of the carrier ring, the connector is in the socket, the optical fibers has one end coupled to the connector, the other end coupled to the fiber array connector, and is coupled to the PIC through the fiber array connector; the cover plate is located on the carrier ring and extends inwardly to above the PIC.

Pluggable optical packing structure

An alignment structure of an optical element includes an optical fiber having a parallel fiber segment and a plurality of bare fiber segments, a cover plate provided with a plurality of side-by-side guide grooves and a plurality of first coupling parts, the bare fiber segments of the optical fiber being arranged in the corresponding guide grooves, cross-sectional shapes of the guide grooves being at least one of U-shaped or V-shaped, and a silicon chip provided with lines and a plurality of second coupling parts. When the cover plate is matched with the silicon chip, the first coupling parts and the second coupling parts are coupled and positioned with each other respectively, and the optical fiber is fixed between the silicon chip and the cover plate.

Alignment structure of optical element

An assembly alignment structure for optical component includes an optical fiber, comprising: a combined fiber segment and a plurality of bare fiber segments; a cover plate, having a first installation surface disposed with a plurality of guide grooves, an installation groove, and at least one first coupling groove, the bare fiber segments being in the corresponding in the guide grooves; a lens, arranged in the installation groove; a chip, having a signal receiving surface; a carrier plate, having a second installation surface disposed with at least one second coupling groove, the chip being fixed on the second installation surface; and at least one positioning post; wherein when the cover plate and carrier plate are aligned, the positioning post is located in the first and second coupling grooves, and the optical fiber and the lens are fixed and aligned between the carrier plate and the cover plate.

Assembly alignment structure for optical component

An optical probe package structure is provided, used in a test environment for testing a plurality of optical chips on a wafer, including: a main body, an optical fiber, an optical fiber positioning area, a mode field conversion waveguide structure, and an optical waveguide. Wherein, the mode field conversion waveguide structure is used to convert the propagation field of the optical signal, and the optical signal transmitted by the mode field conversion waveguide structure enters the optical waveguide. The optical waveguide has an emitting end, and the emitting end is provided with a facet, the facet has a facet angle, and the facet angle makes the optical signal after field conversion mode field conversion to produce total reflection and output along a second direction. The optical signal after total reflection enters the optical chips. Thereby, an optical probe package structure that can test before wafer cutting and polishing is provided.

Optical probe package structure

An alignment structure of optical element is provided, including: an optical fiber, having a parallel fiber segment and a plurality of bare fiber segments; a cover plate, provided with a plurality of side-by-side guide grooves and a plurality of first coupling parts, the bare fiber segments of the optical fiber being arranged in the corresponding guide grooves, cross-sectional shapes of the guide grooves being at least one of U-shaped or V-shaped; and a silicon chip, provided with lines and a plurality of second coupling parts; when the cover plate is matched with the silicon chip, the first coupling parts and the second coupling parts being coupled and positioned with each other respectively, and the optical fiber being fixed between the silicon chip and the cover plate. As such, precise positioning and rapid assembly are achieved.

An optical probe for optoelectronic integrated circuits is provided, applicable to a test environment for testing a plurality of optical chips on a wafer. The optical chips include at least one optical waveguide, and the optical probe includes a substrate and an optical fiber. The facet of the optical fiber has a first angle, and the first angle causes the optical signal transmitted by the optical fiber to generate total reflection, and the optical signal after total reflection enters the optical waveguide of the optical chip. Thereby, an optical probe able to perform testing before wafer cutting and polishing is provided, and a high-speed, effective and reliable detection is achieved.

Optical probe for optoelectronic integrated circuits

Provided is a memory structure including first and second transistors, an isolation structure, a conductive layer and a capacitor. Each of the first and second transistors includes a gate disposed on the substrate and source/drain regions disposed in the substrate. The isolation structure is disposed in the substrate between the first and second transistors. The conductive layer is disposed above the first and second transistors and includes a circuit portion electrically connected to the first and second transistors and a dummy portion located above the isolation structure. The capacitor is disposed between the first and second transistors. The capacitor includes a body portion and first and second extension portions. The first and second extension portions extend from the body portion to the source/drain regions of the first and the second transistors, respectively. The first and second extension portions are disposed between the circuit portion and the dummy portion, respectively.

Memory structure

Provided is a memory structure including first and second transistors, an isolation structure, a conductive layer, and a capacitor. The first transistor and the second transistor are disposed on a substrate. Each of the first and second transistors includes a gate disposed on the substrate and two source/drain regions disposed in the substrate. The isolation structure is disposed in the substrate between the first and the second transistors. The conductive layer is disposed above the first transistor and the second transistor, and includes a circuit portion, a first dummy portion, and a second dummy portion, wherein the circuit portion is electrically connected to the first transistor and the second transistor, the first dummy portion is located above the first transistor, and the second dummy portion is located above the second transistor. The capacitor is disposed on the substrate and located between the first dummy portion and the second dummy portion.

A training system and method of object detection model is disclosed. The training system includes an object detection model and a loss calculation module. The object detection model is configured to generate an output image according to an input image. The loss calculation module, coupled to the object detection model, is configured to calculate a total classification loss value according to the output image and a solution image, calculate a loss value according to the total classification loss value, and transmit the loss value to the object detection model. The total classification loss value is calculated according to a number of classification losses corresponding to a number of object types. Each classification loss corresponding to each object type is calculated according to a first parameter, a second parameter and a third parameter.

Training method and system of objects detection model based on adaptive annotation design

A memory structure including first and second transistors, an isolation structure and a capacitor and a manufacturing method thereof are provided. The first and second transistors are disposed on the substrate. The isolation structure is disposed in the substrate between the first and second transistors. The capacitor is disposed between the first and second transistors. The capacitor includes a body portion and first and second extension portions. The first and second extensions are extended from the body portion into the substrate at two sides of the isolation structure and connected to the source/drain regions of the first and the second transistors, respectively. The widths of first and second extension portions are decreased downward from a top surface of the isolation structure.

Memory structure having transistors and capacitor and manufacturing method thereof

Provided is a memory structure including first and second transistors, an isolation structure, a conductive layer and a capacitor. Each of the first and second transistors includes a gate disposed on the substrate and source/drain regions disposed in the substrate. The isolation structure is disposed in the substrate between the first and second transistors. The conductive layer is disposed above the first and second transistors and includes a circuit portion and a dummy portion. The circuit portion is electrically connected to the first and second transistors. The dummy portion is located above the isolation structure. The capacitor is disposed between the first and second transistors. The capacitor includes a body portion and first and second extension portions. The first and second extension portions extend from the body portion to the source/drain regions of the first and the second transistors, respectively. The first and second extension portions are disposed between the circuit portion and the dummy portion, respectively.

Growing community of inventors

Hsinchu, Taiwan

Po-Yi Wu