Faraday Technology Corporation

Po-Wen Hsiao

Chih-Hung Wu

Ko-Ching Chao

Zhou-Lun Liou

A method and apparatus for performing self-calibration of receiver offset without shorting differential input terminals of a receiver are provided. The self-calibration includes: inputting input signals carrying predetermined data patterns into a plurality of receivers; performing data eye width measurement on the input signals received by the plurality of receivers to obtain multiple first data eye widths and multiple second data eye widths respectively corresponding to first and second data bytes; performing first offset calibration to make the multiple first data eye widths converge to a first common data eye width; performing second offset calibration to make the multiple second data eye widths be equal to the multiple first data eye widths, respectively, and converge to the first common data eye width; and performing reference voltage calibration on a reference voltage to optimize the multiple first data eye widths and the multiple second data eye widths.

Apparatus and method for performing self-calibration of receiver offset without shorting differential input terminals of receiver

A method for performing divided-clock phase synchronization in a multi-divided-clock system, an associated synchronization control circuit, an associated synchronization control sub-circuit and an associated electronic device are provided. The method may include: performing frequency division operations according to a source clock to generate a first divided clock and a second divided clock; performing phase relationship detection on the first divided clock according to the second divided clock to generate a phase relationship detection result signal; performing a logic operation on a first phase selection result output signal and the phase relationship detection result signal to generate a second phase selection result output signal; and outputting one of the second divided clock and an inverted signal of the second divided clock according to the second phase selection result output signal, for further use in a physical layer circuit.

Method for performing divided-clock phase synchronization in multi-divided-clock system, synchronization control circuit, synchronization control sub-circuit, and electronic device

Growing community of inventors

Hsin-Chu, Taiwan

Po-Wen Hsiao