Taiwan Semiconductor Manufacturing Comp. Ltd.

E Ink Holdings Inc.

Po-Wei Chen

Wen-Chung Tang

Chung-Cheng Chen

Yu-Lin Hsu

Kuan-Yi Lin

Ming-Sung Kuo

Chien-Li Kuo

Yu-Wen Chen

Chun-Yu Lu

Yu-Chieh Hung

Shih-Hsiang Tai

Scott Liu

Hsun-Kuo Hsiao

Fang-yu Liu

Ping-Cheng Ko

Jhih-Yuan Yang

Min-Sung Kuo

I-Kai Hung

A measurement pattern for monitoring overlay shift of bonded wafers includes a top wafer pattern and a bottom wafer pattern. The top wafer pattern includes a first portion with a width Wx1 measured along a first axis. The bottom wafer pattern includes a first part with a width Wx2 measured along the first axis, wherein the first portion of the top wafer pattern and the first part of the bottom wafer pattern are separated by a target distance Dx, and wherein the measurement pattern satisfies the following measurement formulas:

Method for measuring overlay shift of bonded wafers

Semiconductor devices and methods of manufacture are provided whereby fences are formed over a substrate and III-V materials are grown over the substrate, wherein the fences block growth of the III-V materials. As such, smaller areas of the III-V materials are grown, thereby preventing stresses that occur with the growth of larger sheets.

Semiconductor devices and methods of manufacture

A measurement pattern for monitoring overlay shift of bonded wafers includes a top wafer pattern and a bottom wafer pattern. The top wafer pattern includes a first portion with a width Wxmeasured along a first axis. The bottom wafer pattern includes a first part with a width Wxmeasured along the first axis, wherein the first portion of the top wafer pattern and the first part of the bottom wafer pattern are separated by a target distance Dx, and wherein the measurement pattern satisfies the following measurement formulas:2;1;

Measurement pattern and method for measuring overlay shift of bonded wafers

The present disclosure relates to a transistor device having source and drain regions within a substrate. A gate electrode is between the source and drain regions. A spacer has a lower lateral portion along an upper surface of the substrate between the gate electrode and the drain region, a vertical portion extending along a sidewall of the gate electrode, and an upper lateral portion extending from the vertical portion to an outermost sidewall directly over the gate electrode. A field plate is disposed along an upper surface and a sidewall of the spacer and is separated from the gate electrode and the substrate by the spacer. A first ILD layer overlies the substrate, the gate electrode, and the field plate. A first conductive contact has opposing outermost sidewalls intersecting a first horizontally extending surface of the field plate between the gate electrode and the drain region.

Thin poly field plate design

An apparatus for storing and transporting semiconductor elements includes a first portion and a second portion. The first portion includes a first front side wall, a first rear side wall, a top wall, and at least one pin holder integrally extending from the first rear side wall. The second portion includes a second front side wall, a second rear side wall, a bottom wall, and at least one pivotal pin structure integrally coupled with and extending from the second rear side wall. The at least one pivotal pin structure comprises a shaft, and a head connected with the shaft. The at least one pin holder defines a cavity sized and shaped to accept the head of the at least one pivotal pin structure. The first portion and the second portion are pivotally movable between an open configuration and a closed container configuration.

Apparatus for storing and transporting semiconductor elements, and method of making the same

The present disclosure relates to a high voltage transistor device having a thin polysilicon film field plate, and an associated method of formation. In some embodiments, the high voltage transistor device has a gate electrode disposed between source and drain regions and separated from a substrate by a gate dielectric. A spacer is disposed along an upper surface of the substrate. The spacer extends along a first gate sidewall closer to the drain region, crosses over an upper edge of the gate electrode, and further extends laterally to cover a portion of an upper surface of the gate electrode. A field plate including a polysilicon thin film is disposed along upper and sidewall surfaces of the spacer so that the polysilicon thin film is separated from the gate electrode and the substrate by the spacer. The thin polysilicon film field plate improves the breakdown voltage of the transistor device.

An organic thin film transistor includes a substrate, a source/drain layer that is located on the substrate and has a source region and a drain region, a first buffer layer that is located between the source region and the drain region, a semiconductor layer that is located on the source/drain layer and the first buffer layer, a gate insulating layer, and a gate electrode. The first buffer layer covers at least one portion of the source region and at least one portion of the drain region. The first buffer layer is located among the semiconductor layer, the source region, the drain region, and the substrate. The gate insulating layer covers the source/drain layer and the semiconductor layer. The gate electrode is located on the gate insulating layer, and a portion of the gate insulating layer is located between the gate electrode and the semiconductor layer.

Organic thin film transistor

An organic thin film transistor includes a drain electrode, a semiconductor layer, a source electrode, a gate insulator, and a gate electrode. A horizontal portion and a vertical portion of the semiconductor layer are respectively located on a top surface and an end surface of the drain electrode, and the drain electrode protrudes from the horizontal portion in a first direction. The source electrode is disposed along a surface of the semiconductor layer. The source electrode has an extending portion that extends in a second direction opposite to the first direction. The gate insulator is disposed along a top surface and two side surfaces of a stacked structure defined by the drain electrode, the semiconductor layer, and the source electrode. The gate electrode is located on the gate insulator, and a portion of the gate insulator is between the stacked structure and the gate electrode.

Display device and organic thin film transistor including semiconductor layer having L-shaped cross-section

A flexible display device includes a flexible substrate, an inorganic barrier layer, a metal layer, an organic buffer layer, and an insulating layer. The inorganic barrier layer is located on the flexible substrate. The metal layer is located on the inorganic barrier layer and in contact with the inorganic barrier layer. The organic buffer layer covers the inorganic barrier layer and the metal layer, and has at least one conductive via connected to the metal layer. The insulating layer is located on the organic buffer layer.

Growing community of inventors

Hsinchu, Taiwan

Po-Wei Chen