Industrial Technology Research Institute

Po-Tsung Tu

Po-Chun Yeh

Jung-Tse Tsai

Chien-Hua Hsu

An enhancement mode GaN transistor is provided, which includes a GaN layer, a quantum well structure, a gate, a source a drain and a first barrier layer. The quantum well structure is disposed on the upper surface of the GaN layer. The gate is disposed on the quantum well structure. The source is disposed on one end of the upper surface of the GaN layer. The drain is disposed on the other end of the upper surface of the GaN layer. The first barrier layer is disposed on the upper surface of the GaN layer and extends to the lateral surfaces of the quantum well structure.

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Tainan, Taiwan

Po-Tsung Tu