Lsi Logic Corporation

Amati Communications Corporation

Po Tong

Peter A Ruetz

John A Bingham

John Matthew Cioffi

James T Aslanis

Antoinette H Gooch

A method of coordinating very high speed bi-directional data transmissions between a central unit and a plurality of remote units over distinct twisted pair transmission lines that share a binder is described. Specifically, periodic synchronized upstream and downstream communication periods are provided that do not overlap with one another. The upstream and downstream communication periods for all of the wires that share a binder are synchronized. With this arrangement, all of the very high speed transmissions within the same binder are synchronized and time division duplexed such that downstream communications are not transmitted at times that overlap with the transmission of upstream communications. In some embodiments, quiet periods are provided to separate the upstream and downstream communication periods. The described invention may be used in conjunction with a wide variety of modulation schemes, including both multi-carrier and single carrier transmission schemes. It is backwards compatible with existing systems and has particular advantages in very high performance systems.

Time division duplexed high speed data transmission system and method

A convolutional interleaving process which utilizes an addressing scheme that enables the amount of memory to be used in the convolutional interleaving process to be reduced is disclosed. A stream of data is convolutionally interleaved at a designated interleaving depth and a designated interleaving block length such that a first symbol in a designated block has an associated predetermined delay and each subsequent symbol in the designated block has a delay equal to more than its predecessor symbol. A plurality of delay related arrays, as well as an initial value array, a lower limit array, and an upper limit array, are calculated in order to define interleaving orbits. The convolutional interleaving process is accomplished by a convolutional interleaver which is arranged to take an incoming stream of data and output an interleaved stream of bits which is conceptually partitioned into blocks. A convolutional deinterleaving process, which is similar to the convolutional interleaving process is also disclosed.

Efficient address generation for convolutional interleaving using a

A transmission system using multicarrier modulation applies FECC (forward error correcting code) coding and codeword interleaving differently to input signals from a plurality of different data channels to produce encoded data signals having different reliabilities and different coding delays. Bits of encoded data signals having relatively less delay are allocated to carriers that are subject to relatively more attenuation and/or channel noise, and hence that are allocated fewer bits for transmission in each symbol period, to reduce the effects of impulse noise. The data channels can comprise video, data, and control channels transmitted on an ADSL (asymmetric digital subscriber line) two-wire telephone line.

Multicarrier modulation transmission system with variable delay

A power sum computation unit for a Reed-Solomon decoder having r redundant symbols and in which a code word, R, has a first plurality (n) of symbols, each symbol having a plurality (m) of bits, including multiplier unit for multiplying in parallel M symbols by powers of a finite field element, .alpha., to obtain the power sums ##EQU2## The multiplier unit includes M multipliers for multiplying M symbols by powers of alpha, and memory delay including a latch, a random access memory, and a flipflop store symbols and sequentially provide M symbols to the multiplier unit. Exclusive OR gate selectively connects products from the multiplier unit and data input words to the memory delay. A counter is provided for the random access memory with the counter having a modulo number equal to one less than r/M, and the random access memory having a depth equal to one less than r/M.

Reed-solomon decoder using discrete time delay in power sum computation

Sequential encoding of Reed-Solomon codes using a discrete time delay line, a single adder, and a single multiplier provides efficient encoding of Reed-Solomon codes with or without interleaving. The encoder utilizes a clock whose rate is r times the symbol rate where r is the redundancy of the code. The finite field operations are performed in a sequential manner requiring only one finite field multiplier and one finite field adder. All memory elements are consolidated into a discrete time delay line which can be implemented with a random access memory. The encoder can be easily reconfigured for changes in generator polynomial of the code, the amount of redundancy, and interleaving depth.

Serial data encoder

A structure and a method are provided for fast-decoding a Huffman code using means for recognizing the number of leading 1's in the Huffman codeword up to a predetermined maximum, and means for removing from the Huffman codeword the number of leading 1's recognized. In one embodiment, both JPEG Huffman code AC and DC tables are stored in a random access memory (RAM). In that embodiment, to access the AC code tables, an address is formed by the number of leading 1's recognized and the portion of Huffman code with the number of leading 1's recognized removed. To access the DC code tables, an address is formed by a predetermined code pattern and the Huffman codeword.

Method and apparatus for decoding Huffman codes

A method and a structure are provided for decoding Huffman codes using a random access memory having a size less than twice the total number of codewords decodable. Under this method, the number of leading 1's in a Huffman codeword and the bits of the Huftman code word other than the leading 1's ('remainder') are combined to form an address into the random access memory. Using the fact that, for a given number of leading 1's in a Huffman code, the possible remainder of the Huffman code is no longer than a predetermined number of bits, the size of the random access memory necessary for decoding such Huffman codes can be made optimally small.

Method and structure for decoding Huffman codes using leading ones

A structure and a method are provided for fast-decoding a Huffman code using a leading 1's detector for recognizing the number of leading 1's in the Huffman codeword up to a predetermined maximum, so as to provide a class number in accordance with the number of leading 1's recognized, a first logic circuit for providing a 'remainder' by removing from the Huffman codeword a number of bits in accordance with the class number, and a second logic circuit for recognizing a special class. In one embodiment, decoding is accomplished by accessing a storage device using an address formed by a table number, a subclass number derived from the class number and all of the bits in the remainder except the least significant bit.

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Fremont, CA, United States of America

Po Tong