Taiwan Semiconductor Manufacturing Comp. Ltd.

Po-Tao Chu

Kun-Ming Huang

Shen-Ping Wang

Lieh-Chuan Chen

Chien-Li Kuo

Chih-Heng Shen

Chun-Yi Yang

Jheng-Sheng You

Hsin-Chih Lin

Ming-Hong Chang

Fu-Hsiung Yang

Long-Shih Lin

Tsai-Feng Yang

Tai-I Yang

Hong-Seng Shue

Tzu-Ming Huang

Che-Yi Lin

Kuang-Hui Chang

Chia-Yuan Chen

Hung-Jen Lu

Ming-Hsien Lee

Ming-Yi Lin

Shao-Chi Yu

Ching-Wen Cho

Chung-Cheng Chen

Tzu-Min Peng

Shou-Wei Lee

Cheng-Ming Wu

Yuan-Chang Huang

Fang-Cheng Chen

Yu-Chieh Chou

Sen-Fu Chen

Ming-Che Yang

Chih-Yuan Chan

Chih-Chien Hung

Chia-Hung Lai

Hsin-Yuan Chen

Chia-Chia Kan

Cheng-Fu Hsu

Chung-Jen Chen

Ming-Chieh Yeh

Kuan-Hui Chang

Tzu-Cheng Chen

Tai-Ming Yang

Ting-Yih Lu

Chaur Rong Chang

Shin-Kuei Yen

Shih Kuei Yen

An integrated circuit (IC) comprising an enhanced passivation scheme for pad openings and trenches is provided. In some embodiments, an interlayer dielectric (ILD) layer covers a substrate and at least partially defines a trench. The trench extends through the ILD layer from a top of the ILD layer to the substrate. A conductive pad overlies the ILD layer. A first passivation layer overlies the ILD layer and the conductive pad, and further defines a pad opening overlying the conductive pad. A second passivation layer overlies the ILD layer, the conductive pad, and the first passivation layer, and further lines sidewalls of the first passivation layer in the pad opening and sidewalls of the ILD layer in the trench. Further, the second passivation layer has a low permeability for moisture or vapor relative to the ILD layer.

Passivation scheme for pad openings and trenches

A device includes a first III-V compound layer, a second III-V compound layer, source and drain structures, a gate structure, and a gate field plate. The second III-V compound layer is over the first III-V compound layer. The source and drain structures are over the second III-V compound layer and spaced apart from each other. The gate structure is over the second III-V compound layer and between the source and drain structures. The gate field plate is over the second III-V compound. From a top view the gate field plate forms a strip pattern interposing a stripe pattern of the gate structure and a stripe pattern of the drain structure.

Semiconductor device

A device includes a first III-V compound layer, a second III-V compound layer, a dielectric layer, a contact, a metal-containing layer, and a metal contact. The second III-V compound layer is over the first III-V compound layer. The dielectric layer is over the second III-V compound layer. The contact extends through the dielectric layer to the second III-V compound layer. The contact is in contact with a top surface of the dielectric layer and an inner sidewall of the dielectric layer. The metal-containing layer is over and in contact with the contact, and a portion of the metal-containing layer is directly above the dielectric layer. The metal contact is over and in contact with the metal-containing layer.

A high electron mobility transistor (HEMT) includes a first III-V compound layer, a second III-V compound layer over the first III-V compound layer, source and drain structures over the second III-V compound layer and spaced apart from each other, a gate structure over the second III-V compound layer and between the source and drain structures, a gate field plate over the second III-V compound layer and between the gate structure and the drain structure, and an etch stop layer over the drain structure and spaced apart from the gate field plate.

A bipolar transistor includes a substrate having a first well with a first dopant type; and a split collector region in the substrate, the split collector region including a highly doped central region having the first dopant type, and a lightly doped peripheral region having a second dopant type, opposite the first dopant type, wherein the lightly doped peripheral region surrounds the highly doped central region, a dopant concentration of the lightly doped peripheral region ranges from about 5&#xd7;10ions/cmto about 5&#xd7;10ions/cm, and the lightly doped peripheral region has a same maximum depth as the highly doped central region.

Method of making bipolar transistor

The present disclosure, in some embodiments, relates to a method of transporting a semiconductor wafer. The method includes transferring a semiconductor wafer into a first wafer slot of a second plurality of wafer slots within an adaptive inset. The adaptive inset is arranged within an interior cavity of a wafer cassette having a first plurality of wafer slots while transferring the semiconductor wafer into the first wafer slot. The wafer cassette and the adaptive inset are transported into a loading port of a semiconductor processing tool configured to perform a fabrication process on the semiconductor wafer.

Adaptive inset for wafer cassette system

The present disclosure, in some embodiments, relates to a wafer cassette system. The wafer cassette system includes a wafer cassette includes a first plurality of wafer slots respectively having a first width. An adaptive inset is fastened to the wafer cassette in a rigid connection. The adaptive inset includes a second plurality of wafer slots respectively having a second width that is less than the first width. The second plurality of wafer slots are configured to receive a substrate after the adaptive inset has been fastened to the wafer cassette.

A group III-V device structure is provided. The group III-V device structure includes a channel layer formed over a substrate and an active layer formed over the channel layer. The group III-V device structure also includes a gate structure formed over the active layer and a source electrode and a drain electrode formed over the active layer. The source electrode and the drain electrode are formed on opposite sides of the gate structure. The group III-V device structure further includes a through via structure formed through the channel layer, the active layer and a portion of the substrate, and the through via structure is electrically connected to the source electrode or the drain electrode.

Group III-V device structure

The method comprises forming a drain region in the first layer. The drain region is formed comprising a drain rectangular portion having a first end and a second end, a first drain end portion contiguous with the drain rectangular portion and extending from the first end of the drain rectangular portion away from a center of the drain region, and a second drain end portion contiguous with the drain rectangular portion and extending from the second end of the drain rectangular portion away from the center of the drain region. The method also comprises forming a source region free from contact with and surrounding the drain region in the first layer.

Ultra high voltage semiconductor device with electrostatic discharge capabilities

A method of making a bipolar transistor includes patterning a first photoresist over a collector region of the bipolar transistor, the first photoresist defining a first opening. The method further includes performing a first implantation process through the first opening. The method further includes patterning a second photoresist over the collector region, the second photoresist defining a second opening different from the first opening. The method further includes performing a second implantation process through the second opening, wherein a dopant concentration resulting from the second implantation process is different from a dopant concentration resulting from the first implantation process.

A semiconductor device includes a first III-V compound layer, a second III-V compound layer over the first III-V compound layer, a source contact and a drain contact over the second III-V compound layer, a gate contact over the second III-V compound layer and between the source contact and the drain contact, a gate field plate over the second III-V compound layer, a first etch stop layer over the source contact, and a second etch stop layer over the drain contact and separated from the first etch stop layer.

The present disclosure relates to a wafer cassette system having an adaptive inset configured to enable wafers having a first diameter to be held by a wafer cassette configured to hold wafers having a second diameter larger than the first diameter. The wafer cassette system includes a wafer cassette having a first plurality of wafer slots configured to receive one or more wafers having a first diameter. An adaptive inset is arranged in an interior cavity of the wafer cassette. The adaptive inset has a second plurality of wafer slots configured to receive one or more wafers having a second diameter that is less than the first diameter. The adaptive inset allows for the wafer cassette to hold wafers having the second diameter, thereby enabling semiconductor processing tools to processes wafer having a different diameter than those able to be held by wafer cassettes that the tools can receive.

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Taipei, Taiwan

Po-Tao Chu