Advanced Semiconductor Engineering, Inc.

Po-Shu Peng

Cheng-Lin Ho

Chih-Cheng Lee

Chih Cheng Lee

Li Chuan Tsai

A substrate includes a first dielectric layer having a first surface and a second surface opposite to the first surface, a first patterned conductive layer adjacent to the first surface of the first dielectric layer and comprising an interconnection structure, and an interconnection element. The interconnection element extends from the first surface of the first dielectric layer to the second surface of the first dielectric layer and is surrounded by the interconnection structure.

Semiconductor device package and a method of manufacturing the same

A semiconductor substrate includes a multi-layered structure, a component and a first conductive via. The multi-layered structure includes a plurality of dielectric layers and a plurality of patterned conductive layers. A topmost patterned conductive layer of the patterned conductive layers is embedded in a topmost dielectric layer of the dielectric layers. The component is embedded in the multi-layered structure. The first conductive via is electrically connected to the component and one of the patterned conductive layers. At least one of the patterned conductive layers is located at a depth spanning between a top surface of the passive layer and a bottom surface of the component

Semiconductor substrate including embedded component and method of manufacturing the same

A package substrate includes a dielectric layer, a conductive via disposed in the dielectric layer, and a conductive pattern layer exposed from a first surface of the dielectric layer. The conductive pattern layer includes traces and a via land, the via land extends into the conductive via, and a circumferential portion of the via land is encompassed by the conductive via. A method of making a package substrate includes forming a conductive pattern layer including traces and a via land, providing a dielectric layer to cover the conductive pattern layer, and forming a via hole. Forming the via hole is performed by removing a portion of the dielectric layer and exposing a bottom surface of the via land and at least a portion of a side surface of the via land. A conductive material is applied into the via hole to form a conductive via covering the via land.

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Kaohsiung, Taiwan

Po-Shu Peng